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Garcia-Lasheras
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Async inside?
Garcia-Lasheras   2/10/2014 10:07:08 AM
@Rick: Maybe it's just me, but I believe that Intel is starting to take advantage from its mostly unsung asynchronous logic IP and Know-How dominance.

This idea is sparking into my head after reading the description in this column of two of the papers that are going to be presented. These are...


"The approach leverages process variations that create unique delays when passing through a circuit array."

Building a deterministic delay by creating custom logic arrays plus balancing the gate capacitive loads is a well proven asynchronous logic technique -- and of course, coding information with custom delays is inherently asynchronous.

 

"a 256 node on-chip network offering 20.2 Tbits/second of aggregate bandwidth. It uses packet-switching techniques to set up a link and circuit switching to stream data between nodes."

The more I think about this, the more I recall an old-school flagship asynchronous company: Fulcrum Microsystems. This company was born in the year 2000 from Caltech and was using asynchronous IP mostly based in the work of the async logic pioneer and guru Alain Martin for building high-performance data switching chips. The point is that Intel acquired Fulcrum in 2011... and I've been anxiously waiting for the moment in which Intel would show a product resembling Fulcrum technology!!

 

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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