sdubois:-If I accept your statement that inter-particle tunnelling is the mechanism of conduction for the Crossbar Ag-aSi in its SET (conducting state) then to avoid the reproducibility and reliability problems of one path between particles becoming the single dominant path the volume fraction of silver particles must be well below the 33% volume fraction where the probability of a continuous path becomes 1. This means even before aggregation of the silver ions into the particles that you claim are present the volume fraction will be roughly the same. This would I think also mean that the ions are well separated, so again please explain what you understand the mechanism of aggregation from ions to particles is; unless that is you are suggesting the particle are dragged from the silver intact in some sort of electro-migration process. To make the statement you make that particles are present and you can control the gap between them then you must have some indication of the dimensions of those particles or the gaps. With that information it is possible to calculate the statistical average 3D path length between electrodes as a function of any volume fraction of particles.
If the mechanism of conduction is tunnelling then the electrical (I-V) and thermal characteristics of the conducting state will be MIM type, can you confirm that is the case and if not explain the reasons why.
While across the spectrum of memory effects there are three competing metal "particles" in insulator mechanisms. In order of the electrical resistance of the insulator involved they are: NmRAM Pt-in-SiO, the second Ag-in-aSi and the third partially crystallized chalcogenides. Perhaps you would care to comment on the difference between your work and that of I Wei Chen at U of Pennsylvania on the thin film nano metal memory, (nmRAM), that utilised atomically distributed Pt in a dielectric. In that case the nano metal films were produced as the result of co-deposition where it would have been reasonable to accept surface mobility as the film is formed would provide a means of aggregation into particles if the particle was greater than a single ion. I look forward to your explanation.
So why the low endurance and the 3 volts. The current may not be trap assisted and no eutic with silicon, but traps exist that eventually trap electrons or holes. So, with the need to keep the particle loading just right and the interface accumulation of particles in a preferred electrode, etc., there are some limitations that places your device in a confortable position when competing with limited endurance and low electron count high end FLASH - that is a possible good side. But, as far as embedded and high temperature, low power devices, this is not optimum.
The distance between the particles indeed controls the current through the device. By controlling the gap between the particles we can control the device on-state resistance. Due to the high quality of the a-Si film and the small distance between the particles, the current is tunneling current instead of trap-based.
The filament of Crossbar's RRAM technology is based on metallic nanoparticles in the neutral state. Unlike other oxide-based RRAM, Crossbar's elemental particles are not involving multiple oxidation numbers. Additionally, Crossbar nanoparticles do not form an eutectic with Si. The conduction is not based on traps either. That's in fact a key advantage of Crossbar's technology compared to the oxide based RRAM devices.
Embedded requirements are rather basic: 1) simple, cheap process, 2) logic voltage compatibility, 3) operation not too slow (faster is better). It's easy to propose memories but if the material/process is not already in the foundry for another product, it will be hard to get in.
The author says the following: "A typical RRAM device consists of two metallic electrodes that sandwich a thin dielectric layer serving as the ion transport and storage medium. The exact mechanism differs significantly among the different materials being used, but the common link among all RRAM devices is an electric field or heat causes ionic movements and local structural changes in the storage medium,
which in turn causes a measurable change of the device resistance". The key 3 words are Local Structural Changes. This means many things to many people, but in this context and taking into account the other points in the article, it is clear that the author counts on gross mass transport of ions cause localized defects suitable for electron and hole trapping. Taking into account that these ions are transition metals with multiple oxidation numbers ( depending on charge compensation surrounding the defective clusters) one can imagine that the whole scheme depends on the trap density of the semiconductor to sustain the state oft orange- that is, in the conductive or insulating state. Even assuming that the transition metal is able to be perfectly compensated after many writing operations, it is still very difficult to accept that this device would not age quickly and fatigue the non-conducting state very quickly with temperature cycling. In effect this structural disorganization is not to different from a type of Phase Change Memory. So, the reliability issues, the thermally dependent programming and the random freak bits are of major concern. I cannot accept too easily this approach and others, which depend on heating, structural breakdown and filament or clustering of macroscopic insertions in a host medium. The approach inherent in CeRAM, which we are working on is to have a clean material without filaments and tolerant to polycrystaline nature of the thin film, in so far that a state of conduction or not is completely an inherent property of transition metal oxides. This means that the translationally invariant and highly atom- site localized Mott-like quantum phase transition is the answer to aging effects and it does not involve gross scale mass transfer and heat. The design of a material to achieve this purely electronic Metal Insulator Phase transition is of course the key technology, and one that combines coordination chemistry and device physics. I believe that because many of these devices in the RRAM area were made without this design view, we have all these secondary mass transfer effects that seem to make perfect sense until reliability and repeatability is the focus. I suggest that the author addresses these two concerns as that is what makes or breaks many memory technologies. I also suggest that this area needs a clear understanding that defects are not friends of reliability and much less reliability. Engineering around these problems is one approach, but not here, not in the nanoscale. To beat FLASH with another charge trapping device only buys you so much. How about going all the way and get to the heart of the matter and develop a memory that is fundamentally using the storage states at the electron- electron interaction inherent in the nature of these materials. This is what we set out to do and delivered in CeRAM.
If as the author suggests the conducting filament in the amorphous silicon device consists of "discrete" metal particles. Is he trying to imply that the metal particles are not in contact, that is the volume fraction of metal particles is just below the 33% value where the probability of the first continuous column of metal becomes unity. If so this would suggest in the SET state that conduction through the amorphous silicon between the metal particles plays a role in the providing the total resistance of the conducting filament. If the moving species is in the form of single metal ions are the particles groups of ions that have somehow aggregated into discrete particle forming clusters that are not part of a continuous metallic column and what mechanism drives the aggregation process? Perhaps the author would enlighten us.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.