Clock gating is also supported in most of the clock buffers in Xilinx 7 Series devices, e.g. in global clock buffers (BUFG) and horizontal clock buffers -- a regional clock distribution network -- (BUFH).
You can also select a lot of different clock inputs for each different clock distribution network, including internally generated clocks.
Ther is more info about this in the next user guide:
@Max: "I remember a time when I thought Sun Microsystems would be around for ever ... it's like the old saying goes: "The bigger they are, the harder they fall" -- it was a sad day when they disappeared :-("
Yes, a very sad day. I really loved SUN Microsystem: its technology, both hardware and software, its openness, its advanced research... Some people think that they were too smart, commited and professional for staying alive in these weird days we are living now.
Max, what a cool collection of 3D ICs related blogs. They suppose a pretty nice reading before going to sleep for me now ;-)
By the way, back in 2007, I was trying to launch a project with a big company in order to build a new asynchronous 3D FPGA architecture. The project was really interesting and very smart planned. Unfortunately, those were bad times for the company, and there were rumours about IBM going to buy it -- finally, Oracle was the one which absorbed the company I was dealing with: SUN Microsystems :-(
Jack wrote: 33MHz only gives you 30ns and that doesn't seem very long to get off one IC, across a PCB and on to another.
30 ns is plenty of time if you register inputs and outputs at the I/O pads and have point-to-point connections that are less than 12 inches: clock to out is 5-10 ns, propagation delay is another 5-10 ns including reflections, and setup is maybe 5ns, so plenty of time. A 33 MHz PCI bus has that same 30 ns clock period, and since it's a bus it has slower propagation than point-to-point if there are multiple cards, and requires that some wait state logic be done in the same cycle. People do 66 MHz PCI, though you may need custom logic to meet the timing.