@TechColab: "Surprised the ARM asynchronous processor didn't get mentioned."
Well, this blog is not supposed to be an historical introduction to asynchronous logic, but a discussion about the REAL problems that synchronous logic is facing today. Thus, the main purpose of this text is setting the scene for introducing the Globally-Asynchronous, Locally-Synchronous approach, A.K.A. GALS, a tradeoff between hand-made async communication and synchronous island synthesized with COTS EDA tools.
The point is that the same Manchester University team that built the Amulet, are now one of the most active advocates for the GALS approach and the asynchronous-NoC -- it's worthy to note that Steve Furber, one of the main architects of the original ARM, is one of the leaders of this Manchester async research group... and he lauched the Silistix Spin-Off too, a startup based in async and backed by Intel. but I'm digressing so much...
The real purpose of this blog is starting a logical line of thinking in which the different components and main ideas for building async circuits over COTS FPGAs are introduced and justified. FPGA technology is intended in this framework as an educative platform for learning and playing with REAL async circuits. Next step will be understanding the basic Ivan Sutherland's micropipelines; after that, I'll introduce you an open project full of resources that should be in the logic designer toolbox... and Finally, I promise a mayor and exciting upgrade from one of the greatest gurus on Async: CalTech's Alain J. Martin.
PS. Sorry if I digress too much, but I really loves this topic. I've bet & lost for Async so many times, that now I'm completely aware the next big async thing is really near -- too much lessons learned!!
Moore's Law says nothing about speed and everything about circuit density. Speed WAS a side effect, but that has waned with advanced nodes. The title should read something like "Asynchronous Techniques Push Circuit Speeds to the Physical Limit". A rather obvious statement if you ask me. Asynchronisity (is that even a word?) has nothing to do with and is completely orthogonal to circuit density.
@Max: "Actually... did you know that, in the early days, asynchronous logic was the norm"
In fact, most of the computers that were built in the 50ths and 60ths had asynchronous logic in their inner gears, e.g. ORDVAC, BRLESC II.
As it's explained in this blog, the rise of Moore's law enabled by CMOS technology empowered the synchronous paradigm adoption, but the fall of Moore's law while hitting the nano scale is signaling the beginning of the new Async era!! -- just ask to the Intel guys what is behind most of the papers are presenting this year at ISSCC ;-)
@Max: "I don't know why, but I love the concept of asynchronous logic"
The reason for this is quite simple: this is the way in that Nature works!! Just a couple of examples:
BIOLOGY: asynchronous logic behaves just as a neuronal network, i.e. data Synchronization is handled by local handshaking and feedback.
PHYSICS: Thes synchronous logic paradigm assumes that you can build a clock that ticks at every point in the space --the registers-- at the same time... but this is just impossible, as you cannot build such a physical system due to the limitations imposed by Einstein's Relativity.
And, by the way, I'm really glad of seeing you and me putting the Async Logic into the headlines again together: this is how we get acquainted just a year ago!!
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.