"Several measures of digital technology are improving at exponential rates related to Moore's law, including the size, cost, density and speed of components. Moore himself wrote only about the density of components (or transistors) at minimum cost."
@tpfj: "joore's Law says nothing about speed and everything about circuit density"
Moore law is all about jumping from one process node to the next and the overal exponential advantage. Density, Speed and Power consumption are all related with the transistor shrinking process.
Moore's law is meaningless beyond CMOS or derivatives, as it badly collapses when data communication replaces data processing as the most expensive process in terms of power consumption, propagation delay, occupied layout area and, of course, monetary cost.
Remeber that by just adding cores/logic, you cannot increase the overall performance in General Purpose Programming.
Back in the nineties, CPU were sold by highlighting their clock speed, as this was really the parameter that supposed an advantage in day to day application. e.g. office suite, graphics, boot-up time.
@TechColab: "Surprised the ARM asynchronous processor didn't get mentioned."
Well, this blog is not supposed to be an historical introduction to asynchronous logic, but a discussion about the REAL problems that synchronous logic is facing today. Thus, the main purpose of this text is setting the scene for introducing the Globally-Asynchronous, Locally-Synchronous approach, A.K.A. GALS, a tradeoff between hand-made async communication and synchronous island synthesized with COTS EDA tools.
The point is that the same Manchester University team that built the Amulet, are now one of the most active advocates for the GALS approach and the asynchronous-NoC -- it's worthy to note that Steve Furber, one of the main architects of the original ARM, is one of the leaders of this Manchester async research group... and he lauched the Silistix Spin-Off too, a startup based in async and backed by Intel. but I'm digressing so much...
The real purpose of this blog is starting a logical line of thinking in which the different components and main ideas for building async circuits over COTS FPGAs are introduced and justified. FPGA technology is intended in this framework as an educative platform for learning and playing with REAL async circuits. Next step will be understanding the basic Ivan Sutherland's micropipelines; after that, I'll introduce you an open project full of resources that should be in the logic designer toolbox... and Finally, I promise a mayor and exciting upgrade from one of the greatest gurus on Async: CalTech's Alain J. Martin.
PS. Sorry if I digress too much, but I really loves this topic. I've bet & lost for Async so many times, that now I'm completely aware the next big async thing is really near -- too much lessons learned!!