This GALS idea seems to be just using a similar approach on a chip that is tradionally used on a PCB. The chips on a PCB will probably all be synchronous designs, but they certainly won't all be sharing the same clock tree!
Asynchronous design is interesting at various scales, but I also find wave pipelining interesting (which is sort of related to timing-dependent asynchronous design). It seems neat that one can avoid a pipeline latch by timing more pulse-like signals (waves) such that they do not overlap. Sadly, wave pipelining is a victim of fast clocks, process variation, and other modern factors.
Most likely 3d chips will buy us 1-2 or maybe 3 generations of moore's law(both in density and partially in price). After that prices won't go down(according to zvi orbach from monolitic 3d), and it would be hard to put more layers due to thermal limits.
@betajet I must admit that occurred to me as well. Back in the day I used to deal with strings of modems used to poll terminals. You HAD to have one clock through the whole system or you'd get errors. If anything puts data out faster than something else can accept it, you'll start losing it. You can use buffers to take up phase differences and slight clock slippage but eventually the buffer will over- or under-flow.
If your buffer is big enough and you're only sending bursts of data you can get away with differences, but we're talking big amounts of data here I think?
tpfj wrote: "Moore himself wrote only about the density of components (or transistors)".
Based on that, and the impending proliferation of 3D ICs, are we not extending Moore's law vertically, so to speak? True, the transistors you can fit in one layer are getting limited, but we're still putting more transistors on a chip by putting in more layers.
Max - you're an expert on this, what do you think?
I'm concerned about the GALS (Globally Asynchronous, Locally Synchronous) approach. Aren't you going to have metastability problems with multiple clock islands? Wouldn't one be better off with all islands having the same clock frequency, but with relaxed timing between islands?
@tpfj: "Really what I'm saying is the laws of physics that are currently kicking our asses will unfortunately still apply to asynchronous circuits, and hence should then suffer in similar ways."
I completely agree with you in this point. Indeed, the really worthy advantages comes from other side effects derived from this situation, not from a direct speed advantage.
The main message I pretended to explain, is that our live has been easy as we had not needed to pay attention to datapath internal geometry for a long while by using synchronous design, but now the paradigm has changed and clock starts to be a problem by itself.
The huge clock network in modern ICs sucks as many as 50% of the total power being wasted. For this reason, there are most practical applications of async circuits in RFID cards, in which async MCUs are heavily used.
In addition, the lack of a global clock with a fixed frequency reduces the EMI by orders of magnitude in async parts. For this reason, Async is used too in low power wireless communication modems.
I agree, the trend is collapsing. Surprisingly, Moore's component, ie. circuit density, is the one that is holding out the longest. We lost speed a long time ago, we lost power fairly recently, we are now rapidly losing silicon $ cost (just look to current process node fab and related mask costs). I don't believe that asynchronous circuits will solve this either. Sure they will scoop out all those currently wasted picoseconds on the non-critical synchronous paths as well as any delay savings through flops that will be absent from an asynchronous equivalent design. But realistically, how much of an advantage do you think this will give you against a well balanced (ie many paths near critical speed) sychronous equivalent. I doubt it is double? Also, remember, a synchronous circuit gives you inherent parallism through pipe-lining. How do you achieve the same parallism asychronously? Really what I'm saying is the laws of physics that are currently kicking our asses will unfortunately still apply to asynchronous circuits, and hence should then suffer in similar ways.