Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 3 / 7   >   >>
Garcia-Lasheras
User Rank
Blogger
Re: Moore's law.....
Garcia-Lasheras   2/14/2014 10:08:25 AM
NO RATINGS
@Max: "Did you see my column on Monolithic 3D IC technologies?"

Arghhhh... I missed that one!!! Graphene, 3D ICs... Very, very interesting -- I'm reading it just now!!

Garcia-Lasheras
User Rank
Blogger
Re: I never metastable I liked
Garcia-Lasheras   2/14/2014 10:01:31 AM
NO RATINGS
@Betajet: "The FPGAs I'm familiar with won't let you do this, because the global clocks don't have clock enables"

I should clarify that I'm not trying to endorse the general use of async logic over COTS FPGAs -- but I did it in the past ;-). The point is that FPGAs are a really affordable platform for learning asynchronous techniques, just as they are for learning conventional synchronous logic.

I truly believe that async methodologies are being to be icreasingly used in the future as a way of dealing with the issues associated to deep submicron nodes and new nanoscale technologies.

Now, let me point to a paper I wrote some years ago about the efficient implementation of asynchronous logic over COTS FPGAs. Here, I expose some interesting experimental results on the old and good Xilinx SpartanIII and VirtexIV. Maybe the most interesting ones are the speed reached for both data communication [Mega Data Items per second] and pausable clock generation [MHz] -- I needed to perform some live demos in order to convince some researchers these were true:
  • Spartan III, -4 speed grade: >175 MDI/s, >300 MHz
  • Virtex IV, -4 speed grade: >550 MDI/s, >700 MHz


zeeglen
User Rank
Blogger
Re: I never metastable I liked
zeeglen   2/14/2014 9:54:55 AM
NO RATINGS
>A pausable clock is based in locally generated clock bursts.

Are you describing an independent clock oscillator that starts up on a trigger so there is always a defined and repeatable time between trigger and first clock edge?


Max The Magnificent
User Rank
Blogger
Re: Moore's law.....
Max The Magnificent   2/14/2014 9:50:48 AM
NO RATINGS
@David @Garcia: Did you see my column on Monolithic 3D IC technologies?

Garcia-Lasheras
User Rank
Blogger
Re: I never metastable I liked
Garcia-Lasheras   2/14/2014 9:41:19 AM
NO RATINGS
@jackOfManyTrades: "This GALS idea seems to be just using a similar approach on a chip that is tradionally used on a PCB"

This is a very clever intuition. In some way, today ICs resembles a big system which has been collapsed inside the chip package. For this reason, terms such as "System-on-Chip", "Sytem-in-Package" or "Network-on-Chip" are a common topic in state-of-the-art VLSI design -- and the thing promises to get even more interesting in the future ;-)

Max The Magnificent
User Rank
Blogger
Re: I love asynchronous logic
Max The Magnificent   2/14/2014 9:35:45 AM
NO RATINGS
@Paul A. Clayton ...I also find wave pipelining interesting...

Wow -- I've not heard that term for more than 20 years I think -- I'd forgotten all about it -- when I first heard about that technique, I was really excited ... but then it seemed to fade away...

betajet
User Rank
CEO
Re: I never metastable I liked
betajet   2/14/2014 9:35:12 AM
NO RATINGS
Jack wrote: Interesting - did you design all the ICs as well as the PCB?  ...once signals left the IC, all bets were off.

I designed the contents of the FPGAs.  Actually, as an IC designer you do have some control over the PCB since you provide a "data sheet" that specifies the external timing of the chip: combinational delays, clock to output delays, and setup/hold constraints.  As the chip designer, you promise the PCB designer that if the timing constraints are met the IC will function properly -- no bets about it.

Garcia-Lasheras
User Rank
Blogger
Re: I never metastable I liked
Garcia-Lasheras   2/14/2014 9:34:42 AM
NO RATINGS
@Betajet: "I've always called those "gated clocks", and I used them decades ago with TTL"

A pausable clock is a different concept. As you point out, clock gating implies that you have a clock signal that is always running and waiting for being injected into the clock distribution network.

A pausable clock is based in locally generated clock bursts. This is, there is an specific digital circuitry that is in charge of generating "trigger" signals only when required. In this way, you don't have a "real clock", but a kind of "pulse" generator -- I understand that the "pausable clock" term may lead to some confussion, but I didn't invent it ;-)

Garcia-Lasheras
User Rank
Blogger
Re: I love asynchronous logic
Garcia-Lasheras   2/14/2014 9:21:50 AM
NO RATINGS
@Paul: "Sadly, wave pipelining is a victim of fast clocks, process variation, and other modern factors."

This issues are common for every design in which you must do deterministic timing asumptions. This is one of the reasons because a well known approach to asynchronous design is considered a glitter alternative for the future: the delay insensitive logic.

This kind of circuits are "correct-by-design", as you don't need to make any extra assumption about process variation, timing, etc. In addition, this circuits automatically adapt their performance to environment variations, such as temperature derives or a swinging power supply voltage.

Plus, delay insensitive design can be used in flexible substrates. An interesting example is the 8 bits MCU that Seiko developed some years ago:



 

 

 

betajet
User Rank
CEO
Re: I never metastable I liked
betajet   2/14/2014 9:18:42 AM
NO RATINGS
Garcia-Lasheras wrote: This is what is called a "pausable clock", and it supposes an advantage in power consumption as this is only triggering when the synchronous logic block has an actual work to do.

I've always called those "gated clocks", and I used them decades ago with TTL.  It was easy to do in TTL, because you could make a clock tree from NAND gates instead of inverters and the NAND gates provided a good place to put in a clock enable.  You could also use the output enable of a tri-state driver as a clock gate.  You can do this as a fully synchronous design: when clocks do toggle, they do so at the same time.

The FPGAs I'm familiar with won't let you do this, because the global clocks don't have clock enables [that are visible to the designer].  So if you want to gate clocks, you have to do it through logic that adds skew and I suspect screws up your hold timing so that it's impractical.

Update: See Brian_D's comment below -- Xilinx does have this capability.

<<   <   Page 3 / 7   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Creating a Vetinari Clock Using Antique Analog Meters
Max Maxfield
55 comments
As you may recall, the Mighty Hamster (a.k.a. Mike Field) graced my humble office with a visit a couple of weeks ago. (See All Hail the Mighty Hamster.) While he was here, Hamster noticed ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
11 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
11 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)