Thanks @Max & @Garcia for those explanations. Max, I did not see your 3d ic blog either - a serious problem on EET these days is that if stuff makes it to the home page it is gone within days or less. Fascinating stuff though. How do they make the Vias in the layers?
@Zeeglen: "Sounds similar to a triggered oscillator using an active digital LC delay line"
Yes, the working mechanism is very similar, but in the case of integrated asynchronous circuits, LC delay lines are not an option -- they are just to big and "expensive".
Instead, you must use the intrinsic delay of the logic gates. I order to make accurate logic delay calculations, the best option is using the logical effort theory, developed by Ivan Sutherland and Bob Sproull in the early nineties.
Well, yes, I can specify stuff on a datasheet, but I want to make it as easy as possible for a customer to use my IC. For a start, my ICs would interface to an IC with processor cores on it, which need software. Consequently, the customer isn't going to change that at the drop of a hat because they've invested a lot of money in that software. So, if my IC is not compatible with the processor IC, my IC isn't going to get selected. If I had specified some interface which required the processor IC to be using some sort of balenced, shared clock, sales revenue would have been $0.
Was your PCB full of FGPAs really fully synchronous? 33MHz only gives you 30ns and that doesn't seem very long to get off one IC, across a PCB and on to another. Another path longer than 30ns would then become a Multicycle Path, which IMHO makes the design not fully synchronous (there will be some combination of process corner, voltage, temperature where the path delay is exactly a multiple of 30ns, which is no good unless you have some circuitry to mitigate the resulting metastability). However, I've been designing at the Matlab level for the last 6 years, so perhaps 30ns isn't so short now?
@Zeeglen: "Are you describing an independent clock oscillator that starts up on a trigger so there is always a defined and repeatable time between trigger and first clock edge?"
Well, what I'm describing is a circuit made from logic gates and that includes some "delay" feedback loops -- similar to a ring oscillator, but there are a lot of alternatives for implementing this.
About the defined and repeatable time, this is a very good question. A very clever alternative is having different delay loops, in such a way you can choose the clock period in real time. By this way, you can change the operating speed, but also implement EMI mitigation techniques -- similar to spread spectrum techniques.
@Betajet: "The FPGAs I'm familiar with won't let you do this, because the global clocks don't have clock enables"
I should clarify that I'm not trying to endorse the general use of async logic over COTS FPGAs -- but I did it in the past ;-). The point is that FPGAs are a really affordable platform for learning asynchronous techniques, just as they are for learning conventional synchronous logic.
I truly believe that async methodologies are being to be icreasingly used in the future as a way of dealing with the issues associated to deep submicron nodes and new nanoscale technologies.
Now, let me point to a paper I wrote some years ago about the efficient implementation of asynchronous logic over COTS FPGAs. Here, I expose some interesting experimental results on the old and good Xilinx SpartanIII and VirtexIV. Maybe the most interesting ones are the speed reached for both data communication [Mega Data Items per second] and pausable clock generation [MHz] -- I needed to perform some live demos in order to convince some researchers these were true: