I'm not sure how much memory these processors can support, but it is certainly enough for a major push in the big data space. It's an impressive accompllishment from Intel, and one that ups the ante significantly in this market.
Linear addressing with 64 bits will get you 16 exbibytes. Technically each segement (for segemente archs like x86 or powerPC) should give you this much space for a total of - no of seg x 16 exbibytes. But there tends to be limits on physical addresses so the entite 64 bits may not be available but you can be rest assured that any physical memory that you can add will be within addressable range. Terabytes is nothing for a 64 bit proc. !
But for single address space OSs with persistent objects, 64 bit will not be enough and so we are starting to see 128 bit designs starting.
The multiple terabytes of memory on these new systems are an extraordinary leap from the largest amount of memory I'd ever heard of before (between 8 gigabytes and 64 gigabytes). I'd thought that processor address space was limited. How much addressable memory can these new processors support? This certainly will enable big data operations that were not possible before.
Sometime in the mid-90's, early Pentium Pro days, I went to a talk entitled something to the effect "X86 vs RISC" by Intel Fellow Fred Pollack. He made some interesting observations, one, that it was not totally a technology issue, it was primarily economics. On the technical side he pointed out that even then the RISC architecture was getting more complex. Also, x86 was shedding some of its ISA legacy.
He predicted most x86's architetural rivals would eventually fall, primarily because they would not be able to sufficiently invest in their architectures.
1. Given the volumes, not sure how long Sparc can survive
2. Power is a good story but it will also survive only if the new openPower gains traction. Or Power is also destined for a long slow decline. A pity, since I like the ISA. Our processor was based on it till we switched to Risc-V
3. Actually at a core level, ARM and Intel are meeting each other from opposite directions.
ARM is no longer just a low power story. Its ILP is approaching Intel levels but the SMT story is not clear. A 16 core ARM 64 bit in a 4 x 4 cluster config running at about 2.5G will be a pretty powerful server processor. Add a mesh/crossbar and 4 HMC controllers and your are talking ! This will get the HPC market and the non RAS sensitive Enterprise market.
Haven't heard much about the Cray stuff. I could ask Intel and since we are an HPC customer, Intel will give some info but the NDA would be so tight that I cannot anyway talk about it ! Waiting for new KL stuff to build a few proto boards for our HPC but I plan to use SRIO for that (4x10 or 4x25 for a 40/100G interconnect)
But from what I have seen on the public domain, the new stuff seems to be lower in the cache hierarchy than QPI. Thought I saw a slide somewhere saying it will be a PCIe adapter. But this will add to latency. Can't imagine Intel adding one more controller to the Ring Bus. PCIe anyway does not cut it as an interconnect. QPI will still be the interconnect for the CC stuff. In a nutshell, Intel's plans seem a little fuzzy.
Yes, it seems as though Intel is going on the offense in order to not have to be caught in a reactive stance as ARM comes after its dominating market share in servers. This is a real threat to IBM's Power PC and Oracle's SPARC, but those companies could make some sort of move as well since Intel seems to be going after performance while ARM goes after power-saving.