At SPIE 2008, TSMC published a paper which talked about shot noise for the different lithography technologies and its impact on CD uniformity. EUV already had trouble in this area at 30 nm, so for the 20 nm size applications, it would have a prohibitive impact on minimum dose requirements, as that would drive up the source power requirement many times beyond the currently already difficult-to-reach target level.
The paper title is "Influence of Shot Noise on CDU with DUV, EUV, and E-Beam"
We should look beyound the lithography tool solutions. We should modify the design rule and make relatively simple chips. I think we have already missed the deadline on 7nm EUV with the current source power.
The problems are not only about lithography but much more for example planarization, multiple masks, metrology etc. What i have seen, the cost will increase exponentially but the ROI will be only additive.
Having attended both of the talks referenced in the article I was surprised by the articles optimistic title and tone. I thought the tone of the talks was generally negative. TSMC in particular really called out ASML not only on the source power but the source reliability as well.
I think in general the mood at the conference is skepticism on EUV and a growing confidence that the 14nm, 10nm, 7nm and even 5nm node can be done without it!
Gridded arrays are being adopted by logic greatly simplifying the difficulty of printing patterns.
Self-Aligned Quadruple patterning is being employed today to make cost effective 16nm NAND Flash. The emerging 3D NAND technologies are already producing 1x equivalent class NAND using 50nm lithography.
A number of talks showed novel combinations of multi patterning techniques with shrink technology that could meet logic requirements at least down to the 7nm node.
The next generation of immersion tools currently being introduced is capable of 250 wafers per hour increasing productivity and reducing cost.
Yes the idea of Octuple Patterning with up to 9 cut masks is economically daunting but there are a number of design and process technologies that can likely mitigate a lot of that. Smart designs, shrink techniques, etc. can all reduce the number of cut masks. There is also a lot of work being done on cost reducing multi patterning by simplification and less expensive material and equipment choices.
EUV may still have its day but even without it the industry appears to be positioning itself to move forward.
The drive lasers continue to fall short. Maybe they will reach the 43KW (in Cymer's case) needed, but that's just for minimum commercial viability. The current drive laser technology is far from practical as a means to build towards the cited ~1KW EUV needed for full sustainability of EUVL. Yet the two primary players have both chosen a path of non-interest in a new generation of CO2 laser technology that bypasses the limitations of the current ones. With volumetric extraction about 3 times as high, practically scalable, Helium free with low to no gas usage, coupled with low maintenance requirements and almost unlimited shelf and dynamic lifetime, one would expect such a laser design would be of interest to them.
If the benefits of a vastly improved drive laser is considered unimportant, one wonders just what plans they have made to mitigate not achieving EUVL as envisioned. Maybe they no longer believe in it and are pursuing tracks of which we are not yet aware.
I haven't seen good cost estimates but that is actually my primary area of experitise these days. I am currently working with several lithography and materials experts on detailed comparisons of all of the alternatives.
I can say that Intel has detailed plans through 10nm and they are forecasting that their cost per die is going to continue to go down ~30% for each of the 14nm and 10nm nodes. Intel is a little bit unique at the moment in that they are doing a full srink at 14nm where many foundries are maintaing the same BEOL for 14/16nm that they have at 20nm
It also depends how you define "7 nm". Although it is supposed to be ~14 nm half-pitch by projection from previous nodes, I can't imagine gates accomodating this, for example. Lg hasn't been scaling that fast recently. It seems more likely to be stuck at say, around 20 nm half-pitch (which requires only double patterning), but there could be more layers patterned this way than previous nodes.
It is interesting to compare the history of DUV and EUV.
DUV resolution was improved first by increasing NA (even to >0.85, before immersion possible), then reducing wavelength (248 nm to 193 nm).
So the EUV community should be focusing on increasing NA and the next EUV wavelength (BEUV or 6.7 nm).
I don't what is the current status at SPIE, but if there is still reluctance or lack of consensus to go to higher NA or BEUV, that's already a sign. Even going to NA>0.4 requires re-consideration of the EUV multilayer design which affects the lithography demagnification and the mask infrastructure.
Then the irony will be that the EUV community could begin to support double patterning, triple patterning, etc. at 13.5 nm. Which defeats the current justification to going to EUV. We might be hearing about this next year, in preparation for 7 nm node.
Rick, the only viable option right now is multi-patterning solution. Ofcourse the cost will be very high and the challenges immense but some top level executive would want to make it a marketing sucess.
What about 193i (or nanoimprint as used in disk drives) to form parallel lines and e-beam to cut them and form vias? TSMC has a Mapper prototype system. David Lam is targeting Multibeam for this purpose, rather than rastering a mask, since it has much relaxed overlay/resolution/writing speed requirements compared to rastering the whole wafer.
157 died since it was a lot of investment for relatively little gain in process capability. EUV may start to be in that position, unless it can demonstrate significant capability improvement or cost reduction at the time it would be inserted.
Not sure EETimes attended the same papers I attended. I heard both papers, and spoke with several colleaggue. The consensus was universal: all believed in the Semiconductor Engineering version (link above). The papers were anything but a revival.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.