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rick merritt
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Re: Not your father's PCIe
rick merritt   2/26/2014 11:09:53 PM
@GSMD: So A3Cube's latency of 100 nanoseconds is the same as SRIO--so why do they bother? Game over for them?

rick merritt
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Re: Not your father's PCIe
rick merritt   2/26/2014 10:44:35 AM
@GSMD: Thanks for sharing your expertise.

As I underdstand it, A3Cube is claiming advances in latency, not necessarily throughput. Their goal is to enable a single system image over a variant of PCIe.

What do you think about their latency claims?

interconnect Guy
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Re: Not your father's PCIe
interconnect Guy   2/26/2014 7:54:53 AM
 

Per the RapidIO website:

"The 10xN specification, backward compatible with RapidIO Gen1 and Gen2 systems, supports 10.3125 Gbaud per serial lane"

The 25GB story is:


"RapidIO specifications are under development to support 25...."


Other interconnects are shipping 25Gbaud Now, and yes IP has been available for years, but never full cores for RapidIO (just thin Phy layers) complete cores are available for FPGA's for interconnects like PCIe and Ethernet.


You may have access to information about roadmaps for Gen 3 RapidIO parts, but the the reality is Infiniband, PCIe and Ethernet are shipping these speeds, and have been for sometime in volume.


In Niche applications the second sourcing may not be a issue, but in volume it is.


Freescale and TI support both PCIe and Ethernet. (and older sRIO) (Gen2)


Per the RapidIO Product showcase last Freescale product for sRIO was 2008
 

interconnect Guy
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Re: Not your father's PCIe
interconnect Guy   2/26/2014 5:58:32 AM
sadly RIO or RapidIO is several signaling generations behind, at 10GB/sec  While others are at 27Gb/Sec  (per pair)  and RapidIO switches are single sourced at IDT.

rick merritt
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Not your father's PCIe
rick merritt   2/25/2014 5:32:10 PM
Can a non-stadard PCIe system interconnect gain much traction?

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