DSA is like a more cost-effective multiple patterning method, particularly good for "more than double" patterning of memory arrays or generally gridded features, without using iterations of spacer deposition and etching. There is a more advanced DSA version even for square arrays of contact holes, using triblock (instead of diblock) copolymers. This one-step multiplication is also the same motivation behind the 3D vertical NAND scheme. If planar floating gate NAND wants to (or even could) keep on going, most likely DSA would be a prime patterning candidate. It conceivably could be cheaper than 3D vertical NAND, but we need undisclosed numbers to compare.
Now of course, like any wannabe technology, like EUV or 3D vertical NAND, there are a number of issues to clear out first. For DSA the key one is natural defectivity and non-uniformity. And besides that, the ability to align repeatably (to an edge). Also, is it too thin to be a reliable etch mask?
It's an interesting stopgap that postpones the end of the line for Moore's Law. That's incredibly valuable of course, but doesn't change the need to continue the search for the next device -- the successor to the MOS transistor.
I've heard a bit about DSA from Imec last fall and it was big in the SPIE Litho proram this week. But when I asked people they said it was more of an additive helping technology rather than a significant replacement for something like EUV, so...
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.