Krisi & resition:-I requested from Micron the details of the power dissipation when the chip is operating at its maximum claimed read and write performance to complete my report. So far I have not received any reply. I think with that information it would be a little easier to judge how near the 16Gb device might be to product status or commercial availibility and higher bit densities-only Micron/Sony can really answer that question.
I think what is very important is Micron/Sony with the 16Gb GeCu-Cu bridge device now have a test structure and mask set that should allow other bi-directional NV memory technologies to be quickly evaluated at high bit density. In that role it will help solve the problem of getting laboratory claims for the performance of single or a few NV memory devices, from where ever they come, evaluated at high bit density and any problems in that respect quickly exposed.
Resistion:- On 16Gb reliability nothing was provided in the ISSCC 2014 paper. However, in August 2012 at the Flash Memory Summit, Santa Clara, Amigo (Keiichi) Tsutsui of the Sony Corporation under the heading "Adaptive ReRAM Tecchnology for 2014" presented the results for a 10Gbit memory using the same CuTe copper filament bridge mechanism, with the same 1GB/s read and 200MB/s program performance as the ISSCC device. For that device a program endurance of greater than105 cycles was claimed with data retention of greater than 105 years. I am afraid that rather meagre bit of what might pass as "reliability" data is the best I can offer at the moment; with the caveat that results do not always necessarily transfer between different device structures.
On the subject of verify one important aspect of reliability involves the way in which, with the 16Gb ISSCC device, iterative set is used in relation to the CSP to reduce power. If with write/erase lifetime the number of tries required increases then it would appear to be the power dissipation budget gets compromised.
Shockley 22:- You can never say phase change memory (PCM) is definitely dead, it is alive but at the moment to use a medical acronym more in the DNR phase. There are still a very large number of problems to solve if PCM memory arrays with chip bit densities that are competitive with Flash (say double digit Gb) and with cell sizes in the 10nm to 20nm lithographic range are to appear in the market place. Problems like elevated temperature data retention, element separation, current density, parameter drift, matrix isolation devices and thermal crosstalk, the latter two are very significant if you want to construct a three dimensional, or stacked matrix.
Part of the answer to your question regarding PCM may be found in the reason why now there are so many many different types of RRAM/.ReRAM memory mechanisms, technologies and devices all competing for NV memory top spot. That effort tells you those workers believe there is still an opportunity and PCM has failed. I think there is still a lot of work ahead before something in the form of a competitive product pops out from the wide spectrum of RRAM/ReRAM opportunities. Of the RRAMs the one that interests me the most at the moment is the CeRAM (Correlated electron RAM). If all the performance and fabrication claims for this device can be established by independent third parties then it has to be the favourite to suceed and as a bulk effect it should scale. If Micron/Sony can turn their 16Gb RRAM copper filament based memory cell into a product in short order then (see my EETimes article) they might be onto a winner of sorts. However, I see that device more as a test vehicle for many different types of RRAM technology and should receive support for that reason alone to allow a quick jump from the laboratory claims to high end lithography.
I think as I said in my recent VLSI report in EETimes perhaps the ReRAM/RRAM community would be better served if they focussed their efforts towards on chip embedded memory and from success there build the bit capacity upwards.
I am aware of the Panasonic MN101L which I think was the first embedded ReRAM in the field, I am not sure which ReRAM material they are using. I have not investigated the Philips product. It is the market and designers who will decide and when we see commercial products with them in then we can measure the success.
With respect to TiO2, I think in any device where you build up a concentration gradient of material that can be moved by electrical means relatively easily is likely to suffer from thermal degradation. I am afraid it's a case of dammed if you do dammed if you don't. If you require a high temperature/high energy to write the memory then that's a problem in many other respects, if you have low energy then diffusion might be the elevated temperature data retention problem.
Cost of ReRAM plant at 10-20nm Samsung should know, most of it will be for silicon processing anyway.
>>With respect to TiO2, I think in any device where you build up a concentration gradient of material that can be moved by electrical means relatively easily is likely to suffer from thermal degradation. I am afraid it's a case of dammed if you do dammed if you don't. If you require a high temperature/high energy to write the memory then that's a problem in many other respects, if you have low energy then diffusion might be the elevated temperature data retention problem.<<
So, how would you describe how Flash gets around this dilema. I'm guessing it has to do with the higher level of control you get from the device being a transistor, but I'm not enough of an engineer to say more or be sure I'm right.
It sure sounds like these guys are in for limited success and skies the limit for 3D Flash.
>>Cost of ReRAM plant at 10-20nm Samsung should know, most of it will be for silicon processing anyway.<<
So that's what Intel's paying for a fab nowadays? I hadn't realized the price went up that much.
Shockley22 Is tunneling a high energy process? For ReRAMs/RRAMs we are talking about moving ions and atoms and buiding up concentration gradients. In Flash they are moving electrons and trapping them. I agree at the moment Flash holds all the aces. As I keep saying the only way now a new NV memory has a chance is to start at relatively small bit density embedded with a processor. It might be possible to fully develop, silicon compatibility etc, and really fast new NV ReRAM/RRAM technolgy memory suitable for cache and end run the high density big stuff. That is what I would try and do now if I had the time and resources. I do not think it would be PCM, once bitten twice shy.
Shockley22:- "Time from idea to product was fast." You are right and that is absolutely key point and is a serious measure of likely success of any new technology. Time to product is directly proportional to the number of hidden or unanticipated problems.
Well, at any rate, I think we're running out of time. All you engineers with your noses to the grindstone may not have noticed that we've got too many people and we're running out of oil and oil is what got us here.
Richard Heinberg is a crystal clear presenter:
Peter Wadhams is one of the world's leading sea-ice scientists.
The sea ice crash and petroleum crash are going to hit at about the same time, in the next few years. That's soon.
Just a heads-up. The science is quite interesting, too.
Thanks Nonvolatile, I was not sure if Panasonic used the Ferroelectric NV memory or a RRAM, so I needed to check, thanks again for the clarification. If I am really honest I was also distracted by my new found interest in the link between NV memory and Dentistry, see the other paper. It just goes to show for all those folks working on moving ions and atoms around to make a NV memory if they fail to make the grade there lessons learned might be applicable elswhere. Nothing learned is ever wasted.
Dear Ron - Thank you for your positive reference to CeRAM. Due to some contractual oblications, within 180 days we cannot discuss much about what we are doing. However, since your excellent article on the technology, much has happened. In the integration front, it has been achieved complete ALD deposition. In the device front, we have a third party testing large areas devices with very good results and confirming the key aspect of the technology as being one that has no filaments and has controllable process driven properties to stay as predicted. On the theoretical front, the Mott transition has kept its main ground for description. And, soon, all of this will come out in the literature. Patents have been issued in every major country and broad claims on how to control Mott Transition only switching via establishing a well passivated CO-doped TMO, has been well established. Switching and disproportionationation have been shown without ambiguity in XPS data. That is, in NiO, we have spectra for On state, showing Ni(+2) dominance, and off state, showing (Ni+3 and Ni+1, dominance) with a transition energy between states of about 0.7 eV, comparable to the reset/set voltage window in the electrical measurements. Key to this, is that compared with non-doped spectra, and filament spectra, we have, for non-doped, just the Ni+3/Ni+2 insulator. Then, as we create filaments, we meet the normal data of other people in which the device is Ni(+0) rich, showing the metallic nature of NiO after filament creation. We extended results to many materials including TiO based devices. Sorry to report that without double layer or filaments, HfO or WOx and Ta2O3, are not Mott switches as expected. So, the CeRAM concept requires a fine tunning of the material property not native to these TMOs. We understand why and will publish soon. As NiO is still the winner, we focused more on a three prong approach : 1. LArge area - to confirm the science and process options;2. Ultra nano scale with in-plane electrodes, starting at 130 nm and ending at 2 nm line width, via a batch scaled AFM lythography - including 4 pt probes and top views that mimic cross sections with many area and thickness ratios. A laser triggering system is being set up to measure the ultimate switching speed in 2 nm devices etc. and, 3. A foundry focused, completely commercially oriented test demo to qualify the device in embedded applications. 1 and 2 already ongoing and no show stoppers, and 3 under secrecy such that no disclosures will come for a while. No need to sell hard, no VC acceptance from us - all in a real world classical business model with fantastic strategy to reach real applications. So, I would say, that without theatrics, and following the Symetrix style, we are qualifying the technology for commercial use, and securing the scientific and commercial priority of this breakthrough. At 2 nm, if all goes well, we are in a new territory, beyond Moore and yet, not a ga-ga futuristic cloud. It takes time. Our brand of FeRAM was done the same way, it now surpases about 1 Billion chips and it has a quiet and yet secured and real position under Panasonic - from NFC to other applications. Since the first market for CeRAM is IoT, embedded makes sense, and parallel research in the Correlated Electron field in many other applications is ongoing as described above. The capability to do 4 Pt probe in in-plane devices is great, and devices are being tested as we speak. We will put results on the web site as things develop (www.symetrixcorp.com) and after we clear patent/secrecy windows and journal subscription. Please be patient. It is important to remember that RRAM is generally good. But, an RRAM without filaments and electroforming is a big claim, so that, extraordinary claims, needs extraordinary evidence (Carl Sagan), we do not take it lightly the responsibility of delivering a true scientific and commercial breakthrough. Since we are not yong guys with a biz plan to shop to VCs, and this is our second memory and 5th major device being introduced to the market, our business model and business ethics force us to not sell wine before its time.
Micron already had a PCM product, but yanked it off later. One problem is the very high RESET current, or RESET voltage much larger than SET voltage. Other unipolar RRAMs, they don't have the high RESET current, but their RESET is quite slow, much slower than SET.