Most PCB and System designers focus on trying to eliminate hard failures and often overlook user induced soft failures.
Pulse simulator systems for product characterization and qualification techniques were never intended for use by the system design engineer as root-cause analysis and debug tools.
Instead a solution to this problem has adapted EMI/EMC 3D scanning systems in conjunction with injected pulse generator simulators in both "current reconstruction" and transient susceptibility scanning modes to attempt to identify which individual components and nodes actually "feel" the residual and induced transient pulses, how much, and to what effect.
A recent EDN article <http://edn.com/design/test-and-measurement/4427136/Embedded-scanning--The-next-step-in-ESD-detection> takes a look toward the future of ESD scanning/reconstruction technology, including Embedded ESD Scanning.
The author of the article, Jeff Dunnihoo of Pragma Design in Austin, Texas, specializes in interface design and ESD architecture analysis.
Jeff recently presented his EMI/EMC 3D scanning solution to the members and guests of the IEEE Boston Reliability Society and the North East Chapter of the ESD Association.
Generally understood the capacitor to charge or discharge to steady state value, over a time scale of RC. So it effectively slows down the ESD pulse while also damping it and drawing the current. Also recall, no voltage discontinuities allowed on a capacitor.
The problem with using capacitors as ESD protection elements is that to have any clamping effectiveness against the ESD pulse, you need a relatively high cap value... >10nF. Of course, this high of cap will kill the link on higher speed ports (diff pairs). The other issue is that unless the capacitor is physically large (0805 or larger), the capacitor itself could be damaged by the ESD.