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GSMD
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Re: Questions?
GSMD   3/24/2014 1:45:13 PM
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That will work, most pre CCID security dongles are done that way. They installed a s ecurity driver first and then enabled the security driver. Back in 2003 when I first tried it, it was pain since USB enumeration for multiple profile devices was flaky, but now what you suggest will work cleanly.

Problem is that you are restricted to a client server kind of model. If you are OKwith that then USB 3.x will do fine. But if code on the dongle needs to initiate anything, then it does not work. 

Colin Walls
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Re: Questions?
Colin Walls   3/24/2014 1:38:56 PM
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I simply visualized a host program being installed from the USB storage, then it using the FPGA coprocessor.

GSMD
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Re: Questions?
GSMD   3/24/2014 1:34:20 PM
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The only hassle is USB is a master/slave protocol, so everything has to be initiated by the master. So I am trying to propose a variant of Serial rapidIO that uses USB 3.0/3.1 connector and PHY. Tried making USB a peer to peer protocol but it was too much work.

This way the only silicon change is the logical layer, kind of a shim.

USB 3.x would still be carried over SRIO so you have backward app compatibility. But if you use the SRIO protocol yiu have a true peer to peer protocol with message passing or RDMA semantics. The dongle's memory will also be cache coherent with the main system's memory.

Colin Walls
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Re: Questions?
Colin Walls   3/24/2014 11:49:51 AM
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That is a very interesting idea. The USB stick might also behave as a storage device and constain the host [PC, Mac, Linux ...] application that makes use of the "coprocessor". It would raise some interesting class driver issues, but but not insurmountable. If you're at EE Live!, I'd welcome a chat on this topic.

DrFPGA
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Re: Questions?
DrFPGA   3/24/2014 11:42:58 AM
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Yes, application dependent. Are there applications that don't fit efficiently on a standard CPU that might fit better on dedicated hardware connected as a 'stick' via USBV 3.0.

One example would be to have an FPGA co-processor that could be configured for different algorithms. You could stream data to it over the USB connection. If the algorithm needed lots of input data, many parallel processors (you could fit 100s on an FPGA) and a small amount of local memory it could be much faster than using the CPU.

Colin Walls
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Re: Questions?
Colin Walls   3/24/2014 8:22:03 AM
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DrFPGA:  I am not quite sure what you have in mind. Obviously you can create a USB 3.0 enabled device with any amount of computing power. Whether the overhead of the protocol would be too great to offset the advantage of sending off some data for processing is entirely application dependent. 

DrFPGA
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Re: Questions?
DrFPGA   3/23/2014 11:16:35 PM
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I'm interested in the new applications the higher data transfer rate will create. For example, is this fast enough to allow co-processing across the USB 3.0 connection? Could we see USB 3.0 sticks with specialized processors on the stick that would be faster than the host CPU?

JanineLove
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Questions?
JanineLove   3/19/2014 1:52:37 PM
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Anyone else have questions for Colin regarding USB 3.0?

_hm
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CEO
USB 3.0 vs Gigabit ethernet and others
_hm   3/9/2014 2:29:53 PM
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It will also be nice to compare USB3 with gigabit thernet and other similar protocol for embedded applications.

 



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