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Nom_De_Plume
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Decoupling caps
Nom_De_Plume   3/18/2014 5:00:20 PM
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I grew up(?) in the 60,s and 70's and used recycled components from discard PCB's from Ravenscraig Steelworks.

It always troubled me that only one decoupling applied cap on VCC? Why not apply the same principle to VSS? Guess what, regarded as a freak or a loon but the designs worked, particularly the analog.

Old enough now to be tolerated as just an obstinate Curmudgeon, but principles stick like S to a blanket!

James Clerk Maxwell nailed and underpinned our theory, thanks JCM!

xjordanx_#1
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Re: High speed serial link - special requirement
xjordanx_#1   3/17/2014 1:49:12 AM
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Good point. The reference is critical - one of the reasons signals are misread is that the ground and reference are not necessarily stable. More on that in a future blog.

_hm
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High speed serial link - special requirement
_hm   3/16/2014 9:22:43 AM
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New generation of FPGA with serail link at 10gbps and hifger, also needs very specific dc power integrity.

Also do you include DC Reference in dc poewr integrity?

 



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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