Design Con 2015
Breaking News
Oldest First | Newest First | Threaded View
3D Guy
User Rank
3D Guy   3/20/2014 8:13:37 AM
I think there is a small typo. CEA-LETI has been working on nm scale TSVs.

rick merritt
User Rank
rick merritt   3/20/2014 9:15:09 AM
@3-D Guy: Fixed.  Thx.

rick merritt
User Rank
Keep out zones
rick merritt   3/20/2014 9:16:27 AM
How big an issue is this for your design? What tech challenges, if any, are even bigger?

User Rank
Re: Keep out zones
chipmonk0   3/20/2014 12:30:41 PM
 " Separately, Terrazon has shown a design using tungsten TSVs that have a high CTE and thus can eliminate the keep-out zone, Reiter notes. "

this statement is absolutely WRONG.

Tungsten has been used instead of Copper to fill TSV vias because it has a LOWER CTE than Cu, almost similar to Silicon hence unlike Cu almost no mismatch stresses during temperature cycling or any effect on device performance ( therefore very small KOZs and the freedom to disperse TSVs throughout the chip and not just at a central location ).

The company that uses W to fill vias is not Terrazon but TEZZARON

The stress field around a filled TSV depends on the square of the Via Dia, the thermal mismatch strain and the modulus of the fill material. Hence the effort now at LETI and elsewhere to try smaller dia TSVs and fill them with lower Mod materials.

Tungsten filling of vias were chosen to satisfy theory and are already in production for Memory chips. The limitation of W is that can't be too long, hence Cu filled vias are preferred for TSVs in interposers ( 2.5-d ).

BTW did this IITC paper from GloFo report any reliability test results ( e,g. temp. cycling effects on the compressive layer in the vias and ultimately surrounding transistors ) ?

The offer of writing a comprehensive article on 3-d TSV technology for EE Times still stands.


User Rank
Re: Keep out zones
Deepak1982   3/20/2014 12:54:43 PM
TSVs can be used to reduce chip-to-chip wire lengths, or to reduce on-chip global wire lengths. For on-chip global wire length reduction, small TSV area is important due to the high TSV densities. If, instead of 5um TSVs with 7um keep-out zones, you have 5um TSVs with <1um keep-out zone, each TSV moves from taking a ~20um region to taking a ~7um region, which represents a 8-9x area reduction. 

Bottom line: Eliminating the keep-out zone will eventually help TSVs reduce on-chip global wire lengths. 

rick merritt
User Rank
Re: Keep out zones
rick merritt   3/20/2014 7:42:53 PM
@Chipmonk: I'd be happy to get an article on 3-D TSVs from you. Fire at will.

Thanks for noting the problem --NOW FIXED -- in the text re TEZZARON. It was my error in mistaking the company name and mischaracterizing Herb Reiter's comment.

User Rank
Re: Keep out zones
Astronut0   3/21/2014 5:15:24 PM
Good catch, chipmonk0.  Thanks!

Top Comments of the Week
Flash Poll
Like Us on Facebook Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Feast Your Orbs on My Vetinari Clock Prototype
Max Maxfield
Well, I have to admit that I have a great big Cheshire Cat-type grin plastered on my face at the moment, because the prototype for my Vetinari Clock project is now well underway.

Jack Ganssle,

Open Office: Your Fart is My Problem
Jack Ganssle,
A Washington Post article, Google got it wrong. The open-office trend is destroying the workplace, describes how the author's ad agency moved her from a private office to an open space ...

Rich Quinnell

Bloopers Book Helps Improve GUI Development
Rich Quinnell
Courtesy of fellow editor "Max" Maxfield (aka Max the Magnificent), I recently acquired a copy of GUI Bloopers 2.0 by Jeff Johnson of UI Wizards. I found it an interesting read chock full ...

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Special Video Section
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.
Recently formed Architects of Modern Power consortium ...
Specially modified Corvette C7 Stingray responds to ex Indy ...
Avago’s ACPL-K30T is the first solid-state driver qualified ...
NXP launches its line of multi-gate, multifunction, ...
Doug Bailey, VP of marketing at Power Integrations, gives a ...
See how to ease software bring-up with DesignWare IP ...
DesignWare IP Prototyping Kits enable fast software ...
This video explores the LT3086, a new member of our LDO+ ...
In today’s modern electronic systems, the need for power ...