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resistion
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Good breakdown
resistion   3/25/2014 11:35:08 PM
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You never know what the 2X is referring to. Here the WL is 33 nm hp.

AD2010
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Technology node
AD2010   3/26/2014 8:25:20 AM
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Until 4x node, half wordline pitch was the defining parameter for technology node of DRAM.

But since 3x node Samsung and SK-Hynix are using half of the STI pitch as the technology node because it is their smallest feature.

Micron still uses the conventional definition.

In this case, the half  WL pitch is 33 nm  and the  half STI pitch is 26 nm. So it is 2x nm.

Thanks

Arabinda Das

ScottenJ
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Feature Size
ScottenJ   3/26/2014 10:57:14 AM
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It seems to me that since these are 6F2 cells then F = sqrt(A/6).

The 3x process is 38nm and the 2x process is 29nm.

Then there is no more argument over what feature to measure.

AD2010
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6F2 method not fully accurate to detrmine F
AD2010   3/26/2014 11:42:48 AM
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6F2 calculation works well only if the cell layout matches the wordline (WL) and bitline (BL) pitches, which mean the WL pitch is 2F and BL pitch is 3F and the product gives 6F2.

But as it is not a perfect 6F2 layout, because slanted active areas are employed the 6F2 does not work.

For example, if F= 29 nm  as you suggest, then for an ideal 6F2, the device should have

BL: 29 x3= 87 nm but this Samsung 2x nm device has BL =76 nm

Similarly

WL pitch should have been: 29 x 2= 58 nm but the WL pitch measured in this device is 66nm.

DRAM mode was defined by half wordline pitch and since last two generations Samsung is using the minimum litho feature size as their F.   

TanjB
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Re: 6F2 method not fully accurate to detrmine F
TanjB   3/26/2014 12:02:09 PM
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Scotten nailed it.  The nm rating has become meaningless, like GHz on CPUs in the Pentium era.  Time to rethink what is important, not just track the marketing spin of the chip companies.  This is analysis, not marketing, right?

In DRAM the size of the bit cell is the bottom line.  It is interesting to know they nearly halved the size of the bit cell by tweaking all the margins and barely reducing the feature width.  This tells us two things: it really should be a more cost effective chip, and Wow they are struggling to make DRAM smaller in any fundamental way.

It will be interesting to see what the 8Gb chip looks like.  Bigger die maybe?  Maybe improve the ratio of the chip area which is used for memory cells?

AD2010
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Cell area or Memory Density
AD2010   3/26/2014 4:45:58 PM
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The most important point for DRAM is memory density ( total Memory divided by the  cell area).

In the future, cell area will not scale well but the total memory density will probably keep increasing with every technology node.

The difficulty in DRAM scaling comes from the big capacitor that does not scale well.

DRAM has moved from 8F2 to 6F2 and may move to 4F2. Extensive Stacking will increase the memory density. Or Wide IO will be adopted. Packaging will became part of the DRAM road map.



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