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3D Guy
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Intel's cost per transistor different
3D Guy   3/27/2014 6:49:06 PM
Intel's Mark Bohr shows cost per transistor scaling for them upto 10nm. However, fabless vendors like nVidia and Broadcom have been complaining about cost per transistor scaling.

Its commonly known in the industry that TSMC is the only option for 16nm/20nm for most fabless companies (since it has 16nm/20nm yielding and has availability). If TSMC has no competition, it can charge whatever it wants... do you think that is a reason for the disconnect between cost per transistor scaling at TSMC and Intel?

Or do you think the cost difference is cos' of Intel scaling its BEOL between 22nm and 14nm, unlike TSMC?

Or do you think Intel is able to scale better and yield better due to more regular layouts (which use cheaper litho steps)?

From what I'm hearing, the lack of competition for TSMC is a major reason for cost per transistor not scaling for fabless companies. That problem won't be solved with FD-SOI. 

EdwinP0
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40,000 wafers/minute!!!!
EdwinP0   3/27/2014 6:47:54 PM
NO RATINGS
Did you mean 40,000/month?

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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