Word on the street is:
GloFo yields are single digit % @ 20nm - that's why one of their major (and few customers) at 20nm walked away.
Samsung doesn't have capacity since Apple is consuming much of it. They take only big orders and wireless companies are hesitant to use them.
UMC has fallen behind.
Intel doesn't have enough IP blocks, service is bad, they're picky about whom they work with and they impose all kinds of layout restrictions on you.
There's no one else but TSMC at the leading edge. They can pretty much charge whatever they want... That's one of the main reasons fabless companies are complaining about cost per transistor not scaling at the leading edge.
Zvi, when looking at the companies you're involed with - easic , zeno semi and 3d monlithic - they seems to complement each other very well to the point that maybe, chips with easic's model becoming similarly prices to cell based asic, while enjoying much reduced design costs.
A. The best path for the idustry to keep reducing cost from here on is adapt monolithic 3D just as the NV NAND vendors are. A list of the cost benifits associated in monolithic 3D could be found at: <http://www.monolithic3d.com/3d-ic-edge1.html>
B. While the cost per gate do not look good below 28nm it is getting far worst once we account for the embedded SRAM which barly scale, severly impacting the cost of SOC as was detailed in our recent blog: <http://www.eetimes.com/author.asp?section_id=36&doc_id=1321536>
C. Intel was suggested that ultra agressive scaling would provide the solution to the higher wafer costs associated with scaling. It dose not make much sense, and Intel continuing problems with yielding 14nm SOC add doubts.
Unlike foundries there is too much of unknown in respect to Intel to be able to truly response to some of the questions presented by 3D Guy. We did write a detailed blog on this issues: Intel vs. TSMC: An Update - <http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/>