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alex_m1
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Re: Intel's cost per transistor different
alex_m1   3/27/2014 10:11:26 PM
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Or_Bach

> fpga at the cost of standard cell


That's really amazing. Best of luck , hoping to see it soon.

Would you mind explaining how it all combines together , here or maybe in another eetimes post ? i'm sure many would find that interesting.

3D Guy
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Re: Intel's cost per transistor different
3D Guy   3/27/2014 9:21:16 PM
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Word on the street is: GloFo yields are single digit % @ 20nm - that's why one of their major (and few customers) at 20nm walked away. Samsung doesn't have capacity since Apple is consuming much of it. They take only big orders and wireless companies are hesitant to use them. UMC has fallen behind. Intel doesn't have enough IP blocks, service is bad, they're picky about whom they work with and they impose all kinds of layout restrictions on you. There's no one else but TSMC at the leading edge. They can pretty much charge whatever they want... That's one of the main reasons fabless companies are complaining about cost per transistor not scaling at the leading edge.

US Made
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20 is planar
US Made   3/27/2014 9:02:46 PM
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Why 20 is expensive?. supose to be planar? also remember when the masses are there cost will come down...

Or_Bach
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Re: Intel's cost per transistor different
Or_Bach   3/27/2014 8:24:18 PM
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Hi Alex

Yes, and even more so:

Using monolithic 3D technology would enable a field prgramble fabric with costs comptetive with Standard Cell !!

alex_m1
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Re: 40,000 wafers/minute!!!!
alex_m1   3/27/2014 8:17:15 PM
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Rick, Did "The 20nm node faces difficulty achieving low leakage" meant "achieving low cost"?

alex_m1
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Re: Intel's cost per transistor different
alex_m1   3/27/2014 8:15:01 PM
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Zvi, when looking at the companies you're involed with - easic , zeno semi and 3d monlithic - they seems to complement each other very well to the point that maybe, chips with easic's model becoming similarly prices to cell based asic, while enjoying much reduced design costs.


Do you think it's a possbility?

 

Or_Bach
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Re: Intel's cost per transistor different
Or_Bach   3/27/2014 7:57:10 PM
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Few points to add and response as follow:

A. The best path for the idustry to keep reducing cost from here on is adapt monolithic 3D just as the NV NAND vendors are. A list of the cost benifits associated in monolithic 3D could be found at: <http://www.monolithic3d.com/3d-ic-edge1.html>

B. While the cost per gate do not look good below 28nm it is getting far worst once we account for the embedded SRAM which barly scale, severly impacting the cost of SOC as was detailed in our recent blog: <http://www.eetimes.com/author.asp?section_id=36&doc_id=1321536>

C. Intel was suggested that ultra agressive scaling would provide the solution to the higher wafer costs associated with scaling. It dose not make much sense, and Intel continuing problems with yielding 14nm SOC add doubts.

Unlike foundries there is too much of unknown in respect to Intel to be able to truly response to some of the questions presented by 3D Guy. We did write a detailed blog on this issues:  Intel vs. TSMC: An Update - <http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/>

 

rick merritt
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Re: 40,000 wafers/minute!!!!
rick merritt   3/27/2014 7:29:27 PM
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I fixed the "/month" editing error

rick merritt
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Re: Intel's cost per transistor different
rick merritt   3/27/2014 7:26:18 PM
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@3D Guy: Good question.  Handel: I await your answer...

Meanwhile, 3D Guy: Are you saying GloFo/Samsung/IBM and UMC have no foundry 20nm in production?

HJ88
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Re: 40,000 wafers/minute!!!!
HJ88   3/27/2014 7:00:15 PM
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Yes, 40,000 wafers/month.

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