Design Con 2015
Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 4 / 5   >   >>
alex_m1
User Rank
CEO
Re: Intel's cost per transistor different
alex_m1   3/27/2014 10:11:26 PM
NO RATINGS
Or_Bach

> fpga at the cost of standard cell


That's really amazing. Best of luck , hoping to see it soon.

Would you mind explaining how it all combines together , here or maybe in another eetimes post ? i'm sure many would find that interesting.

3D Guy
User Rank
Manager
Re: Intel's cost per transistor different
3D Guy   3/27/2014 9:21:16 PM
NO RATINGS
Word on the street is: GloFo yields are single digit % @ 20nm - that's why one of their major (and few customers) at 20nm walked away. Samsung doesn't have capacity since Apple is consuming much of it. They take only big orders and wireless companies are hesitant to use them. UMC has fallen behind. Intel doesn't have enough IP blocks, service is bad, they're picky about whom they work with and they impose all kinds of layout restrictions on you. There's no one else but TSMC at the leading edge. They can pretty much charge whatever they want... That's one of the main reasons fabless companies are complaining about cost per transistor not scaling at the leading edge.

US Made
User Rank
Rookie
20 is planar
US Made   3/27/2014 9:02:46 PM
NO RATINGS
Why 20 is expensive?. supose to be planar? also remember when the masses are there cost will come down...

Or_Bach
User Rank
Rookie
Re: Intel's cost per transistor different
Or_Bach   3/27/2014 8:24:18 PM
NO RATINGS
Hi Alex

Yes, and even more so:

Using monolithic 3D technology would enable a field prgramble fabric with costs comptetive with Standard Cell !!

alex_m1
User Rank
CEO
Re: 40,000 wafers/minute!!!!
alex_m1   3/27/2014 8:17:15 PM
NO RATINGS
Rick, Did "The 20nm node faces difficulty achieving low leakage" meant "achieving low cost"?

alex_m1
User Rank
CEO
Re: Intel's cost per transistor different
alex_m1   3/27/2014 8:15:01 PM
NO RATINGS
Zvi, when looking at the companies you're involed with - easic , zeno semi and 3d monlithic - they seems to complement each other very well to the point that maybe, chips with easic's model becoming similarly prices to cell based asic, while enjoying much reduced design costs.


Do you think it's a possbility?

 

Or_Bach
User Rank
Rookie
Re: Intel's cost per transistor different
Or_Bach   3/27/2014 7:57:10 PM
NO RATINGS
Few points to add and response as follow:

A. The best path for the idustry to keep reducing cost from here on is adapt monolithic 3D just as the NV NAND vendors are. A list of the cost benifits associated in monolithic 3D could be found at: <http://www.monolithic3d.com/3d-ic-edge1.html>

B. While the cost per gate do not look good below 28nm it is getting far worst once we account for the embedded SRAM which barly scale, severly impacting the cost of SOC as was detailed in our recent blog: <http://www.eetimes.com/author.asp?section_id=36&doc_id=1321536>

C. Intel was suggested that ultra agressive scaling would provide the solution to the higher wafer costs associated with scaling. It dose not make much sense, and Intel continuing problems with yielding 14nm SOC add doubts.

Unlike foundries there is too much of unknown in respect to Intel to be able to truly response to some of the questions presented by 3D Guy. We did write a detailed blog on this issues:  Intel vs. TSMC: An Update - <http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/>

 

rick merritt
User Rank
Author
Re: 40,000 wafers/minute!!!!
rick merritt   3/27/2014 7:29:27 PM
NO RATINGS
I fixed the "/month" editing error

rick merritt
User Rank
Author
Re: Intel's cost per transistor different
rick merritt   3/27/2014 7:26:18 PM
NO RATINGS
@3D Guy: Good question.  Handel: I await your answer...

Meanwhile, 3D Guy: Are you saying GloFo/Samsung/IBM and UMC have no foundry 20nm in production?

HJ88
User Rank
Freelancer
Re: 40,000 wafers/minute!!!!
HJ88   3/27/2014 7:00:15 PM
NO RATINGS
Yes, 40,000 wafers/month.

<<   <   Page 4 / 5   >   >>


Top Comments of the Week
Flash Poll
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
<b><a href=Betajet">

The Circle – The Future's Imperfect in the Present Tense
Betajet
5 comments
The Circle, a satirical, dystopian novel published in 2013 by San Francisco-based writer Dave Eggers, is about a large, very powerful technology company that combines aspects of Google, ...

Max Maxfield

Recommended Reads From the Engineer's Bookshelf
Max Maxfield
27 comments
I'm not sure if I read more than most folks or not, but I do I know that I spend quite a lot of time reading. I hate to be idle, so I always have a book or two somewhere about my person -- ...

Martin Rowe

Make This Engineering Museum a Reality
Martin Rowe
Post a comment
Vincent Valentine is a man on a mission. He wants to make the first house to ever have a telephone into a telephone museum. Without help, it may not happen.

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
16 comments
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Special Video Section
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
10:29
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.
Recently formed Architects of Modern Power consortium ...
Specially modified Corvette C7 Stingray responds to ex Indy ...
Avago’s ACPL-K30T is the first solid-state driver qualified ...
NXP launches its line of multi-gate, multifunction, ...
Doug Bailey, VP of marketing at Power Integrations, gives a ...
See how to ease software bring-up with DesignWare IP ...
DesignWare IP Prototyping Kits enable fast software ...
This video explores the LT3086, a new member of our LDO+ ...
In today’s modern electronic systems, the need for power ...