Regarding the cost of FD-SOI starting wafers: the real price for large volumes is obviously the result of a commercial discussion between the supplier and the buyer, which depends on many factors such as volume and perspectives, strategic agreements, etc. However Soitec has indicated that using 500USD/wafer in volume as a budgetary price makes complete sense (I work for them). Since Handel plans a follow-up, we should see soon the hypothesis he is taking and get indications on why he believes FD-SOI is cheaper than FinFET (I understand the inspection steps required are a key factor).
Regarding wafer prices for FinFETs, there is the need to get gross profit margin of 40% minimum (and better targets are 45% or 50%) to generate funding required for CAPEX and R&D in new generations of technology. The leading foundry vendors are able to get these gross profit margins.
With FinFET wafer cost of $4K and gross profit margin of 45%, wafer price is $7.27K. With gross profit margin of 40%, wafer price is $6.67K.
Competition is good, but wafer manufacturers need to make sufficient profits to be able to continue investing.
In the short term, there can be some discontinuity between wafer prices and cost, but longer term, there needs to be correlation. The most profitable and most price disciplined foundry vendor is TSMC. Samsung is also highly profitable and very disciplined on prices. We have to base price projections on real data.
If you build a plant for $10B (low end of the price range) to crank out one wafer per minute (40,000 per month) and assume flat depreciation over 4 years (by which time that node is trailing edge and a replacement already has been built) that is about 2M wafers, or about $5,000 per wafer. It is reasonable to assume that this is doubled by the investments in new design, masking, and other operational costs for each device running down that line.
The cost of the wafer is material but not dominant. Even the most expensive substrate is less than 10% of the manufacturing contribution to final cost. It is entirely possible that savings such as fewer masks, more familiar device characteristics, and simpler processing could make FDSOI actually cheaper for equivalent high end devices.
A real analysis of cost would include wafer cost, but does not stop there.
@Junko -- news about the Gen2 FDSOI was just posted by Soitec -- see Fig 2 in http://www.advancedsubstratenews.com/2014/03/fd-soi-back-to-basics-for-best-cost-energy-efficiency-and-performance/. It's done with source/drain engineering, and also shows pretty spectacular results at 28nm -- beating 20nm bulk perf for 50% lower cost. While I don't have all the details (and no doubt ST would be part of this) -- such developments would typically involve the whole Albany alliance: ST, IBM, Leti, Soitec, GF, Renesas, so it will be interesting to hear more details about it.
The first graph says as it's main heading "Cost Per Gate" but (and I read it clearly) the Y scale says cost per 100M gates which makes much more sense. It's an interesting challenge, I wonder if 20nm is the last stop for mainstream (based on current transistor technologies)?