Breaking News
Comments
Newest First | Oldest First | Threaded View
Page 1 / 5   >   >>
krisi
User Rank
CEO
Re: 20 is planar
krisi   4/8/2014 10:40:47 AM
NO RATINGS
even for 8-inch the price is low...i guess volume dependent as you say

SOI lady
User Rank
Rookie
Re: 20 is planar
SOI lady   4/8/2014 10:33:02 AM
NO RATINGS
For a 300mm wafer, of course! All depends how many you want....

krisi
User Rank
CEO
Re: 20 is planar
krisi   4/1/2014 7:07:52 PM
NO RATINGS
500USD per wafer is small, even at large volume...is this 12-inch wafer?

krisi
User Rank
CEO
Re: 40,000 wafers/minute!!!!
krisi   4/1/2014 7:05:25 PM
NO RATINGS
I think it was leakage

gzav
User Rank
Rookie
Re: 20 is planar
gzav   3/31/2014 3:29:35 PM
NO RATINGS
Regarding the cost of FD-SOI starting wafers: the real price for large volumes is obviously the result of a commercial discussion between the supplier and the buyer, which depends on many factors such as volume and perspectives, strategic agreements, etc. However Soitec has indicated that using 500USD/wafer in volume as a budgetary price makes complete sense (I work for them).
Since Handel plans a follow-up, we should see soon the hypothesis he is taking and get indications on why he believes FD-SOI is cheaper than FinFET (I understand the inspection steps required are a key factor).



HJ88
User Rank
Freelancer
Re: Intel's cost per transistor different
HJ88   3/31/2014 1:10:09 PM
Regarding wafer prices for FinFETs, there is the need to get gross profit margin of 40% minimum (and better targets are 45% or 50%) to generate funding required for CAPEX and R&D in new generations of technology. The leading foundry vendors are able to get these gross profit margins.

With FinFET wafer cost of $4K and gross profit margin of 45%, wafer price is $7.27K. With gross profit margin of 40%, wafer price is $6.67K.

Competition is good, but wafer manufacturers need to make sufficient profits to be able to continue investing.

In the short term, there can be some discontinuity between wafer prices and cost, but longer term, there needs to be correlation. The most profitable and most price disciplined foundry vendor is TSMC. Samsung is also highly profitable and very disciplined on prices. We have to base price projections on real data.

TanjB
User Rank
Rookie
Re: 20 is planar
TanjB   3/31/2014 11:53:13 AM
NO RATINGS
If you build a plant for $10B (low end of the price range) to crank out one wafer per minute (40,000 per month) and assume flat depreciation over 4 years (by which time that node is trailing edge and a replacement already has been built) that is about 2M wafers, or about $5,000 per wafer.  It is reasonable to assume that this is doubled by the investments in new design, masking, and other operational costs for each device running down that line.

The cost of the wafer is material but not dominant.  Even the most expensive substrate is less than 10% of the manufacturing contribution to final cost.  It is entirely possible that savings such as fewer masks, more familiar device characteristics, and simpler processing could make FDSOI actually cheaper for equivalent high end devices.

A real analysis of cost would include wafer cost, but does not stop there.

junko.yoshida
User Rank
Blogger
Re: Intel's cost per transistor different
junko.yoshida   3/31/2014 11:27:28 AM
NO RATINGS
@Adele, great! Thanks for the link and additional info. I will check it out!

Adele.Hars
User Rank
Rookie
Re: Intel's cost per transistor different
Adele.Hars   3/31/2014 11:12:46 AM
NO RATINGS
@Junko -- news about the Gen2 FDSOI was just posted by Soitec -- see Fig 2 in http://www.advancedsubstratenews.com/2014/03/fd-soi-back-to-basics-for-best-cost-energy-efficiency-and-performance/. It's done with source/drain engineering, and also shows pretty spectacular results at 28nm -- beating 20nm bulk perf for 50% lower cost. While I don't have all the details (and no doubt ST would be part of this) -- such developments would typically involve the whole Albany alliance: ST, IBM, Leti, Soitec, GF, Renesas, so it will be interesting to hear more details about it.

Etmax
User Rank
Rookie
Re: 40,000 wafers/minute!!!!
Etmax   3/31/2014 4:48:07 AM
NO RATINGS
The first graph says as it's main heading "Cost Per Gate" but (and I read it clearly) the Y scale says cost per 100M gates which makes much more sense. It's an interesting challenge, I wonder if 20nm is the last stop for mainstream (based on current transistor technologies)?

Page 1 / 5   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Creating a Vetinari Clock Using Antique Analog Meters
Max Maxfield
18 comments
As you may recall, the Mighty Hamster (a.k.a. Mike Field) graced my humble office with a visit a couple of weeks ago. (See All Hail the Mighty Hamster.) While he was here, Hamster noticed ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
11 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
11 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)