Intel's Mark Bohr shows cost per transistor scaling for them upto 10nm. However, fabless vendors like nVidia and Broadcom have been complaining about cost per transistor scaling.
Its commonly known in the industry that TSMC is the only option for 16nm/20nm for most fabless companies (since it has 16nm/20nm yielding and has availability). If TSMC has no competition, it can charge whatever it wants... do you think that is a reason for the disconnect between cost per transistor scaling at TSMC and Intel?
Or do you think the cost difference is cos' of Intel scaling its BEOL between 22nm and 14nm, unlike TSMC?
Or do you think Intel is able to scale better and yield better due to more regular layouts (which use cheaper litho steps)?
From what I'm hearing, the lack of competition for TSMC is a major reason for cost per transistor not scaling for fabless companies. That problem won't be solved with FD-SOI.
A. The best path for the idustry to keep reducing cost from here on is adapt monolithic 3D just as the NV NAND vendors are. A list of the cost benifits associated in monolithic 3D could be found at: <http://www.monolithic3d.com/3d-ic-edge1.html>
B. While the cost per gate do not look good below 28nm it is getting far worst once we account for the embedded SRAM which barly scale, severly impacting the cost of SOC as was detailed in our recent blog: <http://www.eetimes.com/author.asp?section_id=36&doc_id=1321536>
C. Intel was suggested that ultra agressive scaling would provide the solution to the higher wafer costs associated with scaling. It dose not make much sense, and Intel continuing problems with yielding 14nm SOC add doubts.
Unlike foundries there is too much of unknown in respect to Intel to be able to truly response to some of the questions presented by 3D Guy. We did write a detailed blog on this issues: Intel vs. TSMC: An Update - <http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/>
Zvi, when looking at the companies you're involed with - easic , zeno semi and 3d monlithic - they seems to complement each other very well to the point that maybe, chips with easic's model becoming similarly prices to cell based asic, while enjoying much reduced design costs.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.