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DrFPGA
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New Skill Set?
DrFPGA   4/3/2014 10:11:03 AM
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If we don't get an automatic cost reduction from process scaling I guess we need to create sa new set of skills that allow us to get cost reductions from other areas. Architecture and system design perhaps? Maybe we will also see more tools for helping optimize system architecture for lower cost implementations? Maybe reconfigurable logic will actually let use use a transitior for more than one functions improving cost efficiency?

Anyone have other ideas on where innovation might help us reduce system cost?

Max The Magnificent
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Re: FINALLY : Cavalry to the rescue
Max The Magnificent   3/31/2014 7:18:55 PM
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@chipmonk0: Now that Intel has finally thrown its hat in the ring...

Good point!

chipmonk0
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FINALLY : Cavalry to the rescue
chipmonk0   3/31/2014 11:36:41 AM
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In spite of a lot of hoopla, the introduction of 2.5 and 3-d packaging technologies have been slow because of fragmentation among the players. So far large IDMs like Intel with proven track record of developing and putting technologies into place all on their own had not taken much interest in Package level integration ( System in a Package ) because they had Fabs 2 nodes ahead of the best Foundries and could integrate more economically on a single chip. Now that Intel has finally thrown its hat in the ring ( to integrate their Processor for Altera and Memory chips from others at high Bandwidth ), the pace of development and implementation of 2.5 and 3d will get faster. 



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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