As a not very sophisticated user of native debugging features of ARM chips I am confused at the plethora of facilities in different chip generations. I know that there begin to be standard debugging cells, but it still is tricky to know what's there. FWIW, to preserve my sanity I try to stick to standard toolchain GCC/GDB for Cortex chips from M0 to A8, and as far as I know there is no way to 'introspect' into exactly which capacities are on the platform I am working with at the moment.
This is a problem with ARM in general, for instance for the system peripherals. On Intel, the PCI resources self-identify but on ARM you just have to read the SRM and write down the memory addresses.As a result, the abstraction has to be handled by software, e.g. device trees on Linux, and the result is quite cryptic. The same goes for debugging, but AFAIK there is no standard to describe it in the way device trees describe the I/O peripherals.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.