Jim Handy and I briefly covered 3D NAND a little earlier in another thread. Yes, it would be interesting to see how far it can be developed. I think the key challenge is etching the vias with straight sidewalls to deeper depths.
Shrinking to the 1x, 1y and 1z will become difficult since the number of electrons on the floating gate become smaller and smaller hence the device endurance and reliability will suffer. As none of the previous comment mentioned going 3D id a huge relief in the litho effort of the Fab since we can go back 3-5 generaqtions, a welcoming proposal by the production organization. Of course cost and yield are issues bu tI believe these will be resolved soon.
Absolutely right Jim. Taking a similar example in main memory segment. HMC is far superior in technology than DDR, but due to cost it has still not been able to replace (and most likely in near future also) DDR.
And the comment is more true in memory market. Memory is perhaps the most price elastic market of all semiconductor device. Cost has the very big say here
You hit on the most important point in memory: Nobody wants to pay more for superior performance unless there is absolutely no alternative. That's why the NOR and SRAM markets have shrunk. 3D will not replace 1Z until it's cheaper than 1Z. That could take a while.
You're right on all of your points but one, and that's the manufacturing plant issue. It should only take about 2 years to build a manufacturing facility for a technology if you have the process all worked out. That could be done with technologies that are now in low-volume production: FRAM, PCM, and MRAM.
These technologies can't get cheaper than NAND flash, though, until they move ahead of NAND in process migration, and they aren't even close to that at the moment.
I think when the words new memory technology or alternative memory are bandied around they should be qualified with silicon dependant memory (SDM) or silicon independent memory (SIM), with a further sub qualification for SDM of monolithic or multi-chip packaging (MCP).
A silicon independent memory will require more than just the emergence of a new memory technology it would be something akin to the past when solid state replaced the vacuum tube. Although some sort of optical coupling, even optical processing might be able to remove some of the silicon interface workload in MCP it is difficult to see complete silicon independence for any new or emerging memory technology for some long time ahead.
Because of the existing investment in fabrication equipment, interface knowledge, designs and reliability SDM would appear to be the easiest and most likely route, so far that has not provided an obvious near-term solution, e.g PCM, CbRAM, ReRAM etc in more than 10-12 years. It looks as though SST-MRAM might now be moving centre stage with correlated electron devices (Symetrix and 4DS Inc) offering an interesting latest addition to the list of possibles.
I think the best analogy is to consider Flash memory for the electronics industry as like the internal combustion engine of the automotive industry. Along the way a few variations NAND, NOR for the former, like gasoline and diesel versions for the latter but still requires silicon or four wheels respectively to make it useful.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.