Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.