And be patient... STMicroelectronics will soon be announcing a "major foundry player" that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company's Q4 and FY13 presentation in Paris on January 28th....
Rick, try the FD-SOI Design Community on LinkedIn for more (not just ST) insight. The FDSOI crowd jumps from 28 to 14nm - not bothering w/20nm --altho Handel is a purist w/respect to nomenclature, it seems ;-) -- anyway, when he says 20nm, the FDSOI folks call it 14nm (that's what they're going head-to-head with, after all). Soitec also has good info - see latest ASN on Gen2FDSOI (28nm performance beats 20nm bulk (and costs 50% less); 14nm matches FinFET (at 20% lower cost). http://www.advancedsubstratenews.com/2014/03/fd-soi-back-to-basics-for-best-cost-energy-efficiency-and-performance/. Also CMP has a been seeing good results in their MPW runs - they've got 140+ users of the 28nm FDSOI PDK (which granted, is provided by ST/Leti) -- hear they're pretty pleased with the results they're seeing.
I think no one has disagreed that 28 nm bulk planar is the cheap(est) starting point. Going to FDSOI or FinFET adds cost, and going to 20 nm adds cost. With the added cost of FDSOI or FinFET, the shrink should be beyond 20 nm to make up, but is 14 nm even enough? Especially with increased lithography costs at 14 nm only adding to the costs?
The same situation of 2002/2003, when AMD chose the SOI process for ClawHammer. The problems were numerous, but this decision revealed itself good for AMD, if we see at the recent past. http://www.geek.com/chips/amd-paid-ibm-46-million-to-solve-some-soi-problems-552954/
Today AMD has to do a gamble, and FD-SOI could be a good pick (like Altera and Intel alliance).
Yes, the industry has moved to Finfets to solve the problems with bulk. It's going to be difficult for FDSOI to become mainstream now. A few points:
(1) Yes, Finfets when executed properly give significantly lower wafer costs than FDSOI. That's what I heard from both Intel and TSMC people who made the decision in their respective companies.
(2) SOITEC is known to have significant yield problems getting 5nm or 8nm thin SOI uniformly across the wafer. I heard some bad yield numbers from their employees. The $500 wafer cost assumption is optimistic.
(3) With AMD moving away from SOI and the industry choosing Finfets over FDSOI, SOITEC is in trouble. It's been funding various marketing pushes by hiring consultants and third parties who push SOI... They also fund the SOI consortium. Some of the recent stuff about SOI in the press comes from those efforts. If you speak with decision makers in companies, they say Finfets WHEN EXECUTED WELL, are better, cheaper and more scalable.
(4) SOITEC was formed to commercialize the French Govt's (CEA/LETI's) SOI invention. So, ST Micro, which gets a lot of funding from the French govt, is pushing the technology.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.