TSMC's 16nm technology has a gate length of 30nm or more. Same is Intel's 22nm. The cross sections have been clearly shown in conferences. 10nm platform that you quote also has a gate length of more than 20 nm as will be shown in June.
This is the first time I hear FinFET does not need strain and strain is bad. Please talk to people that run wafers.
Whether it's most of the current in the top or all of it, at the end of the day what matters is current per capacitance or gm divided by capacitance. If you do that math FinFET comes shy. Please see broadcom's invited paper at iedm 2013. FinFET ft - even intrinsic , which is simply 1/2pi gm/Cgs comes worse than 20nm planar.
We can talk all day how beautiful a PowerPoint FinFET is. But the fact is that one by one people are seeing its problems.
Dear Sang Kim. You are making the assumption that 14nm technology needs a 14nm gate length, which is not true. This is know across all companies. The technology node number is just a label, without any direct connection to any dimension on the device.
I agree embedded SiGe is not doable on FDSOI, and that's why I used SiGe in the channel, with performance competing with anything that is out there. However, I do not agree FinFET does not need a strain knob. It does and as far as I have seen (experimentally and by analyzing data from Intel and TSMC so far) eSiGe does NOT work the way it used to. The explanation you provided as only the top of the channel conducting the current actually makes things worse. You are paying the capacitance penalty for the entire gated portion of the fin, so if only the top portion really conducts it's less current for a given capacitance.
I am not sure where you get the 3.5nm thickness from. Although it is a great improvement over 6nm vs 12nm argument you were making not long ago. As publicly stated multiple times and will be shown at VLSI symp in a few months, 14nm FDSOI is using 6nm channel thickness. It uses Si channel for NFET and SiGe for PFET. NONE of the FinFET devices published so far have a strain knob for PFET despite all the performance claim and continue to normalize the current per footprint which I consider cheating as a device engineer - this is exactly how TSMC claimed performance parity or even advantage over Intel 22nm. And by the way there is no 16nm or 14nm gate length in 16nm FinFET technology. The shortest gate length in FinFET is 30nm and low leakage devices go all the way to 50nm. Please see TSMC's paper. Those rule of thumb thickness versus gate length don't come into play when you design technology relevant devices. And believe me I did this for both FinFET and FDSOI for more than 6 years.
IBM uses SOI for its Power processors. Your point is valid: Freescale stopped using SOI because of gaps in the design IP, and AMD also retreated. It is hard to gain back the cost of the wafer for $20 chips, I was told.
"All the industry is going to FinFet, following Intel that has a three years lead and experience"...
Oh sure, I mean Intel has a PERFECT record on process selection, they've NEVER jumped on a technology before it was "ready for prime time" and regretted the consequences, have they? Oh and by the way has anybody seen my bubble memory USB key, I think I must have misplaced it somewhere...hmm!?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.