There are two general categories of radiation effects. There is long term wear out caused by cumulative exposure to ionizing radiation and there are single event effects.
Tolerance to long term exposure effects used to require custom or so-called 'rad-hard' processes. Today, an IC manufuctured with a commercial 28nm CMOS process can tolerate in excess of 1 MegaRAD of exposure. To put that in perspective, a 20 year geo-synchronous satellite mission is exposed to roughly 1 KiloRAD.
There are several different 'single event effects.' All of them are caused by interaction of an IC with an energetic particle. Particles include atmospheric neutrons, protons, alpha particles and cosmic rays or heavy ions. The neutrons are relatively low energy but exist in relevant concentrations at sea levels. Cosmic rays are high energy but are a concern outside the protective magnetic field.
Single-event upsets (or SEU) is the term used to describe the change of state of storage element. SEU is generally getting worse as devices scale but can be combatted via several 'rad tolerant by design' techniques including ECC on an SRAM or triple module redundancy at system, subsystem or cell level.
Ran Ginosar's "Survey of Processors for Space" (2012, PDF) seems to provide a decent overview of methods for tolerating radiation. Basically one can use a radiation hardened manufacturing process (e.g., RAD750), use circuit design techniques that tolerate radiation (radiation hardened by design, e.g., LEON), coarser-grained hardware or software redundancy in space or time with comparisons and retry or voting, or simply tolerate occasional incorrect function. (Obviously, these methods can be combined.)
Thermal stress is another issue more common for computing systems used in space, and, of course, energy efficiency (which is becoming increasing important in non-space use) allows reduced weight for the power source.
The PowerPC was not really designed as a RAD-HARD CPU -- but many of the PowerPC versions are fabricated on a process where the active layers are insulated from the substrate -- (for lower power) -- this also means that high energy particles that strike the substrate(largest cross-section of nuclei ) have much less chance of toggling or disturbing the logic -- Gives the best performance in space for anything running above 1GHZ -- usually they are run in pairs or triplicate because they still can be upset. A big factor is the die size (larger features and larger die = bigger target) (larger features = somewhat harder to toggle a bit (more energy per bit) -- there are a number of different ways to get something that needs to run in a higher radiation environment to work
I'm not the expert on rad hardening, but this is the official press release from NASA.
The most popular CPU selection for most of the missions in the past seems to be PowerPC from what I have heard. Dr. Matthies described the vision processing used during the last Mars landing where the final descent was steered to avoid landing in a bad spot. I had preconceptions of full video processing, but they actually only had time to process a few still images.
I'll look around and see if I can find a copy of his presentation.
"lower voltages and smaller geometries significantly increased the resistance to radiation errors."
Was that a typo? Do you have data backing up this claim?
My understanding is that lower voltages and smaller geometries REDUCE the resistance to radiation errors, ie: for the ICs used in todays smartphones, exposure to radiation will increase the rate of occurence of data errors, compared to the older, larger ICs operating from higher voltages (5V). I have heard that the old 486 was the last IC that US military would accept for radiation hardened applications.
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