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Sanjib.A
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CEO
On chip ESD protection
Sanjib.A   4/20/2014 1:27:09 AM
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"...These signals don't have to drive an external package pin or a trace on a circuit board, and they don't require electrostatic discharge (ESD) protection..."

Is there a ESD protection circuit per pin of a DDR chips available in the market? What kind of level of protection that serves (4KV or more?)? I am not a chip designer but I design boards with these chips. As I understand, the chips interfacing directly to a port accessible to the users or the chips exposed outside the plastic/metal case (product housing) would be prone to ESD risks but I don't think DDR memory chips fall in these category. Well, if we are talking about replacing NAND FLASH chips (cards) with DDR, which could be accessible to the user...I understand that risk.

resistion
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Lots of 3D DRAM options
resistion   4/20/2014 11:19:14 PM
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http://www.3dincites.com/2013/10/the-many-flavors-of-3d-dram/

Maybe HBM seems most flexible and cheapest to handle, as it's a pure DRAM stack connected by TSVs?

Jim Handy01
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Re: On chip ESD protection
Jim Handy01   4/21/2014 2:15:19 PM
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Sanjib,

The ESD on MOS chips (CMOS, PMOS, & NMOS) protects them from damage when they are being handled during shipping and prior to insertion in a PC board.  Back in the old days we used very elaborate precautions to achieve the same thing, like putting foil or a wire around the pins of a device as we soldered it into a PC board.

I don't recall the standards for ESD protection, but it's something like 2kV on a surface equivalent to the surface area of the human body, and it's on every I/O pin of all contemporary MOS chips that I know of.

I have a vague recollection that ESD protection adds 2pF to an I/O pin's capacitance, but don't rely on this figure.

It's on every pin of every device, though.  One advantage of TSVs is that you don't need ESD on every TSV since the chips remain in a more controlled environment until the TSVs are connected to another chip.

Jim Handy01
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Blogger
Re: Lots of 3D DRAM options
Jim Handy01   4/21/2014 2:31:11 PM
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Resistion,

Thanks for the link to Francoise von Trapp's excellent article.

I misunderstood the HBM, thinking that it was a packaged device with logic at the bottom similar to HMC.  I see now that the logic is in the processor that the unpackaged DRAM stack sits on top of.  That poses the same problem as Wide-IO: A cheap DRAM could force an integrator to scrap an expensive processor.

It's early in the game.  I'll certainly be watching to see how it all settles out.

Sanjib.A
User Rank
CEO
Re: On chip ESD protection
Sanjib.A   4/21/2014 11:31:55 PM
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@Jim: Thank you for the information!! Getting rid of the capacitor per pin would greatly help. For the board designer it would help in reducing the efforts in routing traces from processor DRAM controller pins to the DRAM chips. Thanks for helping me in understanding the advantage of sticking the DRAMs with processor fabric through TSVs!!

msporer
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Re: On chip ESD protection
msporer   4/23/2014 2:23:54 PM
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Commodity DRAM are still tested to Human Body Model (HBM) to 2000V discharge since these devices are subject to handling on DIMMs in the field. But ESD risk still exists during chip manufacturing. There is another model for ESD, the Charged Device Model (CDM). CDM occurs when the device itself accumulates a charge and discharges to a low impedance ground in die or packaged form. CDM has the highest discharge rate and can induce damage at lower voltages. So for die which are designed to never be handled by human hands the ESD protection circuits can be significantly reduced, but not eliminated completely.

Jim Handy01
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Re: On chip ESD protection
Jim Handy01   4/24/2014 1:48:07 PM
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msporer

Thanks!

It's always helpful to have an expert chime in.

Jim



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