2. How much power does one of these consume running 1.5 TFLOPS, including the logic needed to get operands to the FPUs?
Also, I sure hope the developers remember to write their floating-point models using single precision, or they're going to get a nasty surprise when they discover that floating-point numbers are not real numbers.
@Betajet: Also, I sure hope the developers remember to write their floating-point models using single precision, or they're going to get a nasty surprise when they discover that floating-point numbers are not real numbers.
If they don;t think of this, then they are silly-billy's of no account. Aslo, if they need double precision for any part of the data path, they can always use the "soft" floating-point approach.
I'm with you on cost.
I keep hoping Xilinx (or Altera) release a low level chip like the Spartan-6, combined with an ARM-M3 or -M4 rather than a Cortex-A.
Cheaper chips can be highly profitable when sold in bulk.
@Max: Thank you for the information! The DSP blocks are not supported on Cyclone V SoCs I suppose? Are these new devices supported on the Quartus II design tool? Does the older versions of the tool support these new SoCs or it would be required to move to a newer version?
The new floating point capabilities are available across the entire Arria 10 family, with density from 160 kLEs to over 1 MLEs. Pricing varies by device density, speed grade, and package. However Altera's Arria10 FPGAs will be priced competitively with other mid-range FPGAs which do not offer this the high performance floating point capabilities of Arria 10.
Power consumption will depend upon the algorithm, the amount and type of I/O needed, amount of on-chip memory and logic used as well as actual GFLOPs. Normally, FPGA designers use the vendor supplied EPE (early power estimator) to estimate their power, using their own design requirements. However, in order to help designers better assess the power used with this new feature, Altera will be providing a number of floating point benchmark designs on Arria 10 development boards in 2H 2014, which will include both GFLOPs and GFLOPs per Watt figures.
True 32 bit single precision floating point numerical representation is supported in the Arria 10 FPGAs. If by "real" numbers, this means double precision floating point (64 bit representation), this can still be implemented in the FPGA. However, since support for double precision is not available in hardened circuitry, it will be implemented in programmable logic and leverage fixed point multipliers. This will result in a substantial increase in logic usage and reduction in performance.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.