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Max The Magnificent
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Re: Half speed
Max The Magnificent   5/29/2014 9:43:46 AM
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@zeeglen: Once - and only once - I proposed similar.  The software people were like to have me strung up, drawn, and quartered for even THINKING such a heretical notion.

I recall a computer in the UK -- you could purchase one with a certain amount of computing power for a certain price -- when your company needed more computing power, you could pay for an upgrade.

The technician would come round and pull out your mother board and plug in a new "super duper" motherboard with "twice the computing power" -- once back in his van, he would take your old board and swap the jumper from 1X clock to 2X clock, then that was the "new" board he would take into the next company...

zeeglen
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Half speed
zeeglen   5/29/2014 9:23:26 AM
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From the article: Running the CPU at half the clock speed, for example, can halve its power consumption.

Once - and only once - I proposed similar.  The software people were like to have me strung up, drawn, and quartered for even THINKING such a heretical notion.

Seriously, this a very informative series of articles, came here from Part 3, don't know how I missed Parts 1 and 2 the first time around.

cuong@edadirect.com
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Monitoring after the board is done is good but does the board have enough copper in the first place?
cuong@edadirect.com   4/25/2014 10:43:01 PM
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This is a great post that should bring awareness to the board designers.  I'd like to supplement the article content by proposing that simulations of the PDN (Power Distribution Network) be done prior to board fab (and during layout) to ensure that there's enough copper in the plane (or thick traces) that need to accomodate high current switching activities.  In today's board design (specifically in the pwr/gnd plane structures) the designer needs to be aware that the pwr/gnd planes can be fragmented due to pin breakouts, via structures, narrow areas, etc...  As such, the full current-carrying effects of the planes cannot be realized.  There could be narrow areas (or neck-down) sections of the plane that must carry the required currents from the regulator to the destination devices.  These types of areas are the bottlenecks in the plane structures and can cause significant (and dynamic) voltage drops when there are high current switching activities from the device power pins connecting to the rail (or GND return paths).  The current will take the path of least resistance (ie. shortest path) to/from the voltage regulator so if these areas are not analyzed correctly there can be areas of high concentration of current density (mA/mil square) that potentially can heat up the traces causing breakdowns over time.  The idea is to have sufficient copper pours to minimize the DC drop (or loss) voltage.  The best way to fix the problem is to avoid it in the first place before the board is fabbed and components are stuffed.  The bench used to be my favorite place to spend time but nowadays I spend more time in simulations than sitting on the bench measuring things.  Simulations can identify issues before the board is fabbed...  Now where would you rather spend time (and money)?



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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