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Tobias Strauch, EDAptix
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Re: Software Defined Peripherals
Tobias Strauch, EDAptix   5/4/2014 10:41:26 AM
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@Crusty,

Well, at a certain point, it is not about how many cores, it is more about, how can you feed them with instructions. When the memory wall reduces the system performance, then you might be better of with less processors. This is what I want to demonstrate with this project as well, that SHP pushes the limitation we have from the memory wall a little bit.

I remember having seen the 6502 on opencores.org. If it turns out to be a stable core, it shouldn't be a big deal to apply SHP on it.

By the way, you might want to tell your good lady wife, that this board will make you really happy. She should have a considerable amount of interest to make you happy, doesn't she ?

Cheers, Tobias

Crusty1
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Re: Software Defined Peripherals
Crusty1   5/4/2014 10:04:23 AM
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Hi Tobias: Now to an old timer like me, how many 6502 cores could you get running on the FPGA at one time.

It might make playing Elite unforgetable? (:-)LOL

Will be backing soon when the good lady wife is not looking at the bank balance.

Regards

Crusty

Tobias Strauch, EDAptix
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Re: Software Defined Peripherals
Tobias Strauch, EDAptix   5/4/2014 9:39:00 AM
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Hi Crusty,

thank you for your kind words.

The initial version is based on the Atmega 2560 (so the full AVR-8 instruction set).

But there are others in the pipe: (MSP430, ARM3,) OpenRISC 1200 and a self designed Cortex M3, but I would like to release the AVR-8 first. You know, this project is not set up to compete with some other guys, it is more about to demonstrate how you can make off-the-shelf CPUs (e.g. opencores.org) more efficient using SHP, that's it. But I guess you know that since our good old APP times.

Cheers, Tobias

Crusty1
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CEO
Re: Software Defined Peripherals
Crusty1   5/4/2014 4:57:20 AM
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Hi Tobias, Tony Tib; Parallax Propellar chip is good but it does require the user to learn yet another implimentation language, at best BST or assembler.

Your approach will at least build on an already large community of Arduino and Atmel knowledge base.

What Atmel chip do you use in your instances?

I will be looking at pledging for a board, as I like the idea of having all those Atmel chips running at the same time in one chip. 

alex_m1
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CEO
Re: Software Defined Peripherals
alex_m1   5/3/2014 12:08:45 PM
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Hi Tobias,

Sorry i came a bit rude. That was not my intention. And best of luck with your project !

 

Tobias Strauch, EDAptix
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Re: Software Defined Peripherals
Tobias Strauch, EDAptix   5/3/2014 7:47:55 AM
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Hi Alex,

I'm not sure if SHP is a very, very known technique – otherwise it would be used more often, I guess. I will unroll the full technology concept of SHP in one of my next blogs on this site. So stay tuned.

So this project is more or less driven by some research fun and the enjoyment you have when analyzing the concept and when you are playing with it in real life. We will see where this all leads to and how it differs from other concepts (like the one you are referring to for instance).

If you like to go with some other concepts, go with it.

If you like to play with a new system architecture and providing suggestions how to improve it (just like some nerds do right now as I pen down these words) then feel welcome and help us by funding this project.

Cheers, Tobias

alex_m1
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CEO
Re: Software Defined Peripherals
alex_m1   5/3/2014 7:03:13 AM
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@Tobias:

But since hyper pipelining is a known technique , whose to say someone like XMOS isn't using it in their chips ? It certainly looks so from their low cost.

So i wonder , whose you're target customer, and what benefits over xmos do you offer him ? one that justify the drawbacks of this against xmos(more expensive, less mature tools, no virtual periperial libraries, much less value in learning this system for experience ) ?

Tobias Strauch, EDAptix
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Re: Software Defined Peripherals
Tobias Strauch, EDAptix   5/3/2014 5:16:15 AM
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@TonyTip "software defined peripherals has been done before"

Well, I never said that I invented virtual peripherals, for sure I didn't. But the point is, that the technology I'm using (System Hyper Pipelining) has many advantages, especially for the system architecture. One out of many potential features is, that it is very, very suitable for virtual peripherals. Only because virtual peripherals are known since the beginning, does that mean I should not optimize the flow for it so user can utilize it.

Tobias Strauch, EDAptix
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Re: What's in a name?
Tobias Strauch, EDAptix   5/3/2014 5:07:02 AM
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@betajet "I've never determined where the product name Arduino comes from"

Guess you have to make more research on where the name is really coming from ;-) Sometimes a letter makes a huge difference.

betajet
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CEO
What's in a name?
betajet   5/2/2014 6:14:15 PM
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I've never determined where the product name Arduino comes from, other than it's an Italian given name or surname.  However, it seems to me it could be derived from the Italian word arduo which means "difficult" or "arduous".  However, -ino is a diminutive suffix so arduino would mean "only a little difficult".

Following this reasoning, arduissimo would mean "really, really difficult".  Not a great marketing concept for an FPGA product IMO :-)

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