Really this is a stepping stone before entering into the 3D era. This step will bring the ever required memory size increase per package as an in-between development before 3D fabrication techniques are ready for manufacturing ICs.
It may not be just cost but also the read current performance. The V-NAND could have a better read current than the smaller silicon channel, but its vertical channel direction could easily get in the way.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.