Dear Sang Kim,
I am not sure what you mean by punch through. There is no leakage path other than the thin channel which is fully controlled by the top gate. I-V characteristics of FDSOI devices have been published in major conferences and there is no sign of degraded electrostatic as you claim. As far as the mobility degradation in thin SOI is concerned, mobility is already hit by high-k gate stack and yet every body is using it. As far as a device delivers the performance why should I care if mobility is higher or lower. Let numbers speak for themselves. We have shown 1.65 mA/um at 1V and 100nA/um for NFET which as far as I know is the highest DC performance ever reported. For PFET drive current is 1.4 mA/um which is again record high. And these are devices at pitch with all parasitic resistances of real technology. And unlike FinFET camp there is no cheating in drive current normalization. I do not want to brag about DC performance as there are many other factors determining circuit performance. But if you are concerned about DC performance please take a moment and review papers in the past few IEDM and VLSI.
The cost for 100M gates of a product made with 14nm FinFET (including 16nm FF+) will range from $1.38 to $1.53 in Q4/2016.
28nm HPC cost per gate will be $0.97 for 100M gates (28nm fab partly depreciated).
For 28nm FD SOI (even allowing for the high cost of the substrate), the cost will be $0.92 for high volume manufacturer. Margins have to be added to get wafer prices from the foundry vendors.
For the high volume applications, cost is the most critical factor followed by power consumption.
The reality is that TSMC and Samsung are very close in their road maps for trying to ramp 16nm FF+ and 14nm FF. While process control is a key factor in bringing up FF products, another critical factor is DFM and impact on parametric yields. It is low parametric yields that have delayed the ramp-up of 14nm FF to date.
Cost per gate is a critical factor, and longer term cost and price do have a relationship.
@OtisTD: Thanks for clarifying. The 28FDSOI is using the flip-well concept (n-well under NFET and p-well under PFET) for LVT devices. RVT is same as bulk design. This allows LVT devices to be forward biased to 1V or maybe more, which is not possible in bulk. If you already have a 28nm bulk design, for static body bias, you can probably just change the well masks, drop the Vt adjust masks, and add the No SOI mask (for diodes, etc).
As far as I know, ST has already implemented dynamic body bias. While it needs some redesign and proper system and software, it is not that different from DVFS to implement. Actually it is a bit simpler because wells do not draw as much current as Vdd does, so charge pumps are enough and routing is easier.
This post is so biased it is difficult to believe.
Saying Samsung is unable to shrink silicon technology when they are leading DRAM and Flash scaling is a joke. Not to mention there lead in display technology. But you may not consider this as "silicon".
Playing the FD-SOI card has nothing to do with failing FinFET. It has specific attribute specially for SOCs and low power technology. And this is where the future of silicon technology will be.
Before considering the fail of FinFET integration within Samsung, just wait by the end of the year...
When I said, I hadn't seen any announcement of "additional body biasing techniques" I meant in addition to what is already available for 28nm bulk. Are you saying that they are offering dynamic body biasing (and where did you see that)? Or just that static body biasing will continue to be offered- which was my intention/understanding. Sorry if I wasn't clear, but I didn't think it was necessary to go into detail. Basically from my understanding they will use the same masks as much as possible and directly port it over FDSOI without adding any additional performance knobs like dynamic biasing.
@OtisTD: Actually, 28nm FDSOI comes with full body bias capability and it is one of its selling points. While people might consider body bias as an extra design burden, many companies - including Samsung in their 28nm bulk - already used static body bias. Dynamic body bias is a bit more involved but it has been done in the past (TI 45nm e.g).
It would depend on the design, but 28nm FDSOI should be pretty comparable to 22nm bulk planar (maybe even better?) from a power vs. performance standpoint. Die size will be bigger, which normally means higher cost, but in this case that isn't so clear. Based on the releases so far the argument in favor of the 28nm FDSOI is that for medium-low TAM products 28nm cost is a sweet spot, there is minimal re-design/re-optimization cost to go to FDSOI, so that offsets the additional substrate cost. The process flow might be a little simpler with FDSOI than with 28nm bulk planar and certainly simpler than 22nm, further offsetting the cost. I haven't seen any indication yet that they will introduce additional body biasing techniques for this 28nm node, but they could and that would further reduce power for some products. Keep in mind Intel has high TAM products that require very high performance- FinFET/TriGate has an advantage there.
In principle it is possible, but it comes at the expense of less design flexibility. The gate and metal pitch at 28nm allows bidirectional poly and metal, whereas Intel's 22nm is unidirectional. A bidirectional M1 is almost equal to 2 layers of unidirectional metal for most designs.
Did Intel fabricate either bulk 22nm to proove FinFET was only 2-3% cost addrer? Did they run FDSOI to see it is 10% cost addrer? No, it was all powerpoint. Same as the famous chart that claimed 37% performance advantage coming from FinFET with no silicon data to back it up -- yes, they actually showed ring ocsilator data at VLSI to support that claim, but I am sure they wish they didn't.