No, the doping is not uniform in bulk planar! The well is retrograde (although not ideal) and there are halos. The whole point is that the well and halo doping will take care of leakage at the depth and gate takes care of it at the surface. I agree with you that the ideal supersteep retrograde will end up with high drain leakage, but that's not the case in FDSOI because drain is isolated from the substrate by the BOX.
BTW, your point about Vt being higher and more variable in a retrograde well is not correct either. In fact it's the other way around! Please see page 230 of Taur and Ning's text book. With retrograde well design Vt is lower than a uniformly doped well and in the extreme case independent of the well doping. This is in fact what SuVolta is promoting. Of course, with Vt being independent of the well doping you cannot use Vt adjust anymore and need to rely on body bias. What FDSOI does is simply making an ideal retrograde well possible and allowing the well doping to have either n+ or p+ polarity for either NFET or PFET witout fearing about drain leakage.
In a bulk planar device with super steep retrograde well, gate only needs to control the top portion of the substrate. Current flow is blocked at deeper locations by the well doping. Similarly in the planar FDSOI gate only needs to control current flow in the SOI layer, below that current is blocked by the BOX. You can imagine an ideal super steep retrograde well device as being to be equal to an FDSOI device with a BOX thickness of zero. Would you say such a device will suffer from pinch through?
At Vg=0, the channel is fully depleted, whether it is in a planar FDSOI or in a FinFET with reasonably low doping. Even in a bulk planar device the top 10-20nm is depleted. That doesn't mean a well-behaved device is in punchthrough wheter it being FDSOI/FinFET/or bulk planar. Your way of describing what seems to be physics is incorrect. I would recommend you consult a text book. Punchthrough happens when gate significantly loses control of the channel and high current folows independent of the gate voltage. This is certainly not the case in all the I-Vs that have been published for sub-30nm gate length FDSOI devices. Drain-induced barrier lowerin (DIBL) is of course inherent to any short channel devices and you CANNOT make it zero. In fact I will argue it does not makes sense to make it smaller than about 100mV/V either.
Your assumption of the gate length needed for a given technology is also incorrect. Gate length has nothing to do with the technology node (and it didn't in the past). At 28nm, FDSOI is using a gate length of 24nm, which is shorter than any alternative at the same node. At 14nm, gate length will be most likely 20-22 nm and so is at 10nm. All needed from gate length is that it fits the required gate pitch and the numbers I quoted above fit the bill perfectly.
Finally, the rule of thumb requirements of the channel thickness for a given gate length are just guidlines. Many other parameters such as gate stack, junction design and BOX thickness affect the electrostatic of the device. This is also the case in FinFET. No one needs 3nm SOI for 14nm FDSOI.
Handel Jones says 28nm FD-SOI is an alternate option
for low leakage, high yields and high performance superior
to 28nm bulk technology. Consequently, Samsung
can support low leakage products with its 28nm FD-SOI.
look at the real issues with FD-SOI. My first question is why
28nm FD-SOI is still not manufactured today by major
semiconductor companies because 28nm bulk is manufactured
for several years by major semiconductor companies today
such as Intel, TSMC, Samsung and others.
In un-doped FD-SOI channel here, with Vg=0V it is possible for drain depletion to extend with large Vdd(1V) to source without inversion. I call this effect punch-through. Therefore, punch-through failure can occur with Vg=0V. On the other hand, with Vg on the drain induced barrier lowering or DIBL leakage current most likely occurs also in un-doped FD-SOI. In order to prevent such DIBL leakage current it is imperative to have an ultra thin SOI channel layer between source and drain so that the drain field can't easily penetrate the ultra thin SOI channel. How thin the ultra thin SOI thickness has to be in order to stop DIBL leakage current? It depends on the channel or gate length, Lg. For shorter Lg, a thinner SOI channel is required.This is the most critical issue for FD-SOI.
For 28nm FD-SOI a 7nm thin SOI channel thickness is required to stop DIBL leakage current. However, the transistor performance becomes significantly degraded due to the transistor mobility degradation because of scattering of charge carriers at the top gate oxide surface and at the bottom SOI surface in the 7nm thin SOI channel. As a result, even if 28nm FD-SOI were manufactured today, it wouldn't be superior to 28nm bulk in terms of transistor performance and manufacturing costs due to significantly higher SOI wafer costs. These are the major reasons why the 28nm FD-SOI is not manufactured today, and will not be either due to punchthough at Vg=0V or DIBL failure while Vg is on.
The other major issue with FD-SOI is its scalerbility. For
20/22nm FD-SOI a 4~5nm SOI channel thickness is required
to stop DIBL leakage current thus further degrading transistor
mobility. Furthermore, it is extremely difficult to control 4~5nm
SOI channel thickness uniformly and reliably across 12 inch
wafers in the manufacturing line. How thin SOI channel
thickness is required for 14nm FD-SOI technology? 3nm! It
Dear Sang Kim,
I am not sure what you mean by punch through. There is no leakage path other than the thin channel which is fully controlled by the top gate. I-V characteristics of FDSOI devices have been published in major conferences and there is no sign of degraded electrostatic as you claim. As far as the mobility degradation in thin SOI is concerned, mobility is already hit by high-k gate stack and yet every body is using it. As far as a device delivers the performance why should I care if mobility is higher or lower. Let numbers speak for themselves. We have shown 1.65 mA/um at 1V and 100nA/um for NFET which as far as I know is the highest DC performance ever reported. For PFET drive current is 1.4 mA/um which is again record high. And these are devices at pitch with all parasitic resistances of real technology. And unlike FinFET camp there is no cheating in drive current normalization. I do not want to brag about DC performance as there are many other factors determining circuit performance. But if you are concerned about DC performance please take a moment and review papers in the past few IEDM and VLSI.
The cost for 100M gates of a product made with 14nm FinFET (including 16nm FF+) will range from $1.38 to $1.53 in Q4/2016.
28nm HPC cost per gate will be $0.97 for 100M gates (28nm fab partly depreciated).
For 28nm FD SOI (even allowing for the high cost of the substrate), the cost will be $0.92 for high volume manufacturer. Margins have to be added to get wafer prices from the foundry vendors.
For the high volume applications, cost is the most critical factor followed by power consumption.
The reality is that TSMC and Samsung are very close in their road maps for trying to ramp 16nm FF+ and 14nm FF. While process control is a key factor in bringing up FF products, another critical factor is DFM and impact on parametric yields. It is low parametric yields that have delayed the ramp-up of 14nm FF to date.
Cost per gate is a critical factor, and longer term cost and price do have a relationship.
@OtisTD: Thanks for clarifying. The 28FDSOI is using the flip-well concept (n-well under NFET and p-well under PFET) for LVT devices. RVT is same as bulk design. This allows LVT devices to be forward biased to 1V or maybe more, which is not possible in bulk. If you already have a 28nm bulk design, for static body bias, you can probably just change the well masks, drop the Vt adjust masks, and add the No SOI mask (for diodes, etc).
As far as I know, ST has already implemented dynamic body bias. While it needs some redesign and proper system and software, it is not that different from DVFS to implement. Actually it is a bit simpler because wells do not draw as much current as Vdd does, so charge pumps are enough and routing is easier.
This post is so biased it is difficult to believe.
Saying Samsung is unable to shrink silicon technology when they are leading DRAM and Flash scaling is a joke. Not to mention there lead in display technology. But you may not consider this as "silicon".
Playing the FD-SOI card has nothing to do with failing FinFET. It has specific attribute specially for SOCs and low power technology. And this is where the future of silicon technology will be.
Before considering the fail of FinFET integration within Samsung, just wait by the end of the year...