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AKH0
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Manager
Re: 28nm FD-SOI
AKH0   8/8/2014 1:56:49 PM
NO RATINGS
1) I do not disagree that the floating body effect affects the transistor characteristics. What I'm saying is that the effect is well known and high performance circuits have been built for over a decade. FYI, IBM's system-z is using SOI and those are bleeding edge performance. The latest was shown at ISSCC 2013, nearly 600mm2 large chip clocking at 5.5GHz. If you think that's not high performance, I have nothing more to say. Floating body effect, self-heat, and whatever "nasty" characteristics you would like to attribute to the PDSOI are there, and yet the whole circuit delivers the performance that is expected.

Scribe line transistors (and other test structures) are characterized to monitor the process. Nobody sells them! So I don't care what type of performance I get in those. As long as I know how they correlate with the overal circuit performance, they serve their purpose.

2) A platform technology is more than a single transistor I-V. It's about all pieces here and there that make it possible to put billions of transistors next to each other. IEDM is about all those pieces not an I-V (that in some cases was not consistnet with the rest of the charts!).

3) Technology name (22nm/28nm etc) is just a label. Look more closely at the papers you read and talks you attend, and you figure they have nothing to do with the gate length. And yes, Intel's gate length was 30nm for lowest Vt and 35nm for higher Vt device.

4) You can have doubts and TSMC has their own reasons. They choose to do FinFET for whatever reason and then ended up postponing it. It's not an easy path and the performance advantage that everyone is claiming is not easy to get. Their plan to do 16FF+ to get more performance is just an indication that 16FF was not competetive, despite what they thought at the beginning.

5) I stand by my earlier comment that at the system level, performnace is not about a single transistor I-V. It's about how many different transistors (SLVT, LVT, RVT, HVT, etc) you have and what kind of Vt range they cover. TSMC rightfully emphasize on this fact in their 28HPM paper. when looking at an Ion-Ioff characteristics this is the information one should be interested to see, the range of Ion and Ioff available and not neccessarily the on current at a given Ioff. A big circuit uses a mixture of transistors withe a range of Vt and it's alway good to have a wider range. Ironically, FinFET has a steeper Ion-Ioff characterstics than a planar device. This means that the abilty to crank up the performance by using a lower Vt device is reduced. Similarily, the ability to increase performance by increasing Vdd when needed is reduced and the ability to drop the leakage by using a longer gate length is reduced.

6) For the record, calling a bulk FinFET is incorrect. Fully depeleted is only meaningful when refering to SOI (as opposed to PDSOI) and does not bear any meaning about the thickness of the device, doped vs undoped channel, etc. Using it to refer to bulk FinFET is a misnomer!

7) In strong inversion, the thickness of the inversion layer is about 3nm in any Si device. That means for anything thicker than this you won't see the effect of the channel thickness. 14nm FDSOI is using 5nm channel thickness with Si for NFET and SiGe channel for PFET. Please read the VLSI'14 paper. The thickness uniformity is not an issue. You start from the same wafer used for 28FDSOI and just oxidize 2nm of Si. If you think thermal oxidation cannot be controlled withing 1A uniformity consult a gate module owner at any company.

8) Enough have said about the performance. NFET PDSOI delivered 1.65mA/um at 100nA/um off current at 1V back in 2012. That's absolute highest performance in any Si NFET. PFET is about 1.4mA/um, again among the highest I've seen. 

 

 

 

 

 

 

 

 

 

 

michigan0
User Rank
CEO
Re: 28nm FD-SOI
michigan0   8/8/2014 12:34:02 PM
NO RATINGS

Dear AKH0

 

Sang Kim

 

1) As I stated previously, PDSOI is completely surrounded by 

SiO2 and has a floating body. As a result, some of electron and

 holes generated during transistor operation are trapped in the 

floating body, adversely impacting transistor electrical transfer 

characteristics such as Vt, DIBLE, subthreshold slope, Id/Vg 

and Id/Vd...etc because there is no substrate for the charge 

carriers to flow through. IBM, AMD and Sony, etc servers with 

PDSOI based circuits have been built, but not for high 

performance. The single transistor I-V is moot? All types of 

single transistors including analog transistors are built in 

wafer scribe lines, and are thoroughly probed, characterized 

and analyzed before the wafer dicing. Self-heating is a big 

issue in PDSOI because the transistor performance degrades 

under high temperatures. 

 

2) If you think that the single transistor I-V is moot, in my 

opinion IEDM is not a good forum for you to attend. Intel's 

22nm dose mean 22nm technology node. It is 22nm FinFET. 

What do you mean by saying that TEM was said to be 30nm? 

Intel 22nm is not 30nm. 30nm is longer than 28nm bulk that 

is in mass production for several years. 

 

3) I doubt that 28nmFDSOI is being manufactured in Crolles 

today and in Samsung next year. Lets wait and see. Why 

the biggest foundry TSMC is not and will not run 28nmFDSOI,

 instead running 16nmFinFET, and production at the end of 

2014 or early 2015. At system or circuit level, even a single 

transistor is very important because circuit is made of single 

transistors. If circuit fails, circuit analysis can't find the cause, 

the failure analysis group dissects the circuit to the transistor 

level and find defects such as particles or measure the 

individual transistor electrical transfer characteristics such as 

Vt, dIBL, dI/dVg ... .etc to determine the root cause of failure. 

Intel FinFET doesn't require the back biasing option to 

improve I-on. Intel FinFET is FDFinFET with no back biasing. 

 

4) For 28nmFDSOI requires 7nm SOI channel thickness. I 

reiterate here. When charge carriers such as electrons and 

holes travel from source to drain in the 7nm thin SOI channel 

layer, they are bound to scatter at the top gate oxide surface 

and at the bottom SOI surface. As a result, the transistor 

mobility degrades, resulting in the transistor performance 

degradation. Possibly an ultra thin 5nm SOI channel 

thickness is required for 22nmFDSOI. The question is can 

we control 5nm thin SOI channel layer uniformly and 

reliably across 12 inch wafers in the manufacturing line? 

For 14nmFDSOI how thin SOI channel thickness is required? 

Possibly 3nm? It appears that 22nmFDSOI is the end of the 

scaling.

 

5) Please clarify why you think 7nm is scary point. At 4nm

 Tsi for FDSOI? See 4) above. 4nm Tsi is not manufacturable. 

FDSOI with 7nm or 5nm channel thickness can not delver a 

competitive drive current yet due to mobility degradation as I 

descrived previously. FDSOI technology is not manufactured 

at any technology node yet while 14nmFinFET will be 

manufactured in late 2014. 

 

I worked for IBM, retired from Intel and hired by Samsung as 

senior adviser for its R/D division. I know very well about IBM, 

Intel and Samsung. I am truly retired several years now.


 



AKH0
User Rank
Manager
Re: 28nm FD-SOI
AKH0   8/1/2014 12:53:11 PM
NO RATINGS
Dear Sang Kim,

1) I agree, PDSOI shows floating body effect which results in history effect in circuits, but this is known for almost two decades and circuits designers know how to handle it. Design of multiple generations of IBM servers and AMD/Freescale/Sony, etc is a estimony that circuits with competetive performance can be made. We can sit here and talk about physics as long as we want, but when there is a chip that runs and delivers the performance, all the discussions about a single transistors I-V are moot. Same applies to the self-heating effect. It is known that when a transistor runs a DC current drive current is about 5% lower because of self-heating. But that condition almost never happens in real circuits except for a few analog transistors. Everything else has an activity factor of 1% or less and self-heating is not an issue.

2) FYI, I have attended IEDM, ISSCC, VLSI, etc and presented in all of them. I think I am well aware of what is being presented at these conferences somethimes well before the conference. For a platform technology, 20nm does not mean anything anymore. It's just a name and has nothing to do with the gate length. When Intel submitted their 22nm paper to VLSI'2012, the minimum gate length from TEM was said to be 30nm. At the conference they showed exact same TEM and called it a 26nm gate length. None of them of course have anything to do with the technology node. When I asked the author about the differences (submission vs presentation) he said one is the physical and one is electrical. His manager however said they had multiple versions of the technology and they just made it shorter. Don't take me wrong, I admire Intel's engineering team and know many of them personally. They did a great job putting the technology together, but that doesn't mean I will not speak up if I do not agree technocally with what they claim.

3) 28FDSOI is being manufactured in Crolles and will be in production in Samsung next year. Circuit level perfrmance have already been demonstrated and that's why it's put in Samsung. If it does not deliver higher performance than 28nm bulk or delivers same performance at a reduced cost, why would any foundry in their right mind want to run wafers? Whay would customers want to spend millions of dollars to design? Again, you and me can talk long about 5nm/7nm, 12" wafers, etc, but circuit designers don't care about any of those. A transistor is a 4 terminal device with a certain I-V and C-V charactersitics for them. At system level, even a single transistor I-V is not important. You care about range of Vt that is available, uniformity across chip and from chip to chip, and the circuit tricks you can play. Body biasing is the strength of FDSOI, that allows you to compensate for variations that you inevetibly have in in any process and adjust the performance for the work load. That option is not available in FinFET. So, yes you get a single transistor with probably higher current with FinFET, but what a circuit designer cares about is the whole device menu and not a single I-V.

4) For 28nm FDSOI the final channel thickness is 7nm, with the starting thickness of 12nm from SOITEC/SEH/SunEdison. The spec is +-5A across wafer and from wafer to wafer and as far as I know all three suppliers do better than that. For 14nm FDSOI (I personally don't agree with the naming, but it has the same gate pitch and metal pitch as 14/16nm FinFET) channel thickness is 6nm and same uniformity spec. You tell me that I cannot start with the same wafer and thermally oxidize 1nm of Si with perfect uniformity? FYI, that was the process used to form the gate oxide before high-k and still is one of the best controlled processes.

5) I think I have measured enough transistors in my life to know if 7nm is scary point or not. If you read publications on mobity in very thin Si, peak mobility drops from ~440 cm2/V.s to maybe 420 at 4nm Tsi. In the presence of high-k peak mobility is less than 200 cm2/V.s. Should the whole industry give up on high-k just because it degrades mobility? At the end of the day what matters is that whether a 7nm or 5nm channel thickness delivers a compeptitive drive current or not. And I think there has been enough publications in the past few years to prove it's doable.

I am a device engineer and for me a good device is a good device, no matter who builds it. FinFET has it's strengths and weakness. Same is bulk planar, FDSOI, or PDSOI. But when looking at a given technology I trust Si data (once confirmed and is consistent across many measurements). The industry does not go anywhere with handwaving arguements based on limited inofrmation and incorrect assumptions.

 

michigan0
User Rank
CEO
Re: 28nm FD-SOI
michigan0   8/1/2014 12:07:58 PM
NO RATINGS

Dear AKH0

 

Sang Kim

 

PDSOI has two major issues: floating body effect because of not 

full depletion and self-heating because the device is totally 

surrounded by the SiO2.As the device is scaled downed to 

22nm, the hot carrier effects are much worse than the 22nm 

bulk. Hot carrier generated holes are trapped in the floating 

body, resulting in Vt shifts instead of flowing toward the 

substrate in case of the bulk.

 

It seems you have not attended IEDM. IEDM stands for 

International Electron Device Meeting, meaning the transistor 

structures presented at IEDM all single transistor devices only 

that include n/p transistor, SOI devices such as PDSOI and 

FDSOI, EPROM, tunneling device and other single devices. 

20nm bulk planar at IEDM means that the distance between 

source and drain is 20nm. Single transistors do not have gate 

pitch and metal pitch. For circuits and system performances 

VLSI and Circuits are right place. Recently, VLSI and Circuit 

conferences are combined.

 

 

what I said about the 28nm FDSOI are: 28nm FDSOI is not 

manufactured today yet, and even manufactured today it 

Would not be superior to 28nm bulk in terms of performance 

and manufacturing costs as I said in my previous posts. I also

said that FDSOI is not scalable. For 28nmFDSOI a 7nm 

SOI channel thickness is required and possibly 5nm for 22nm

FDSOI. How the 5nm SOI channel thickness can be controlled 

uniformly and reliably across 12 inch wafer in the manufacturing 

line? I doubt that Soitec can supply such ultra 

thin 5nm SOI wafer.

 

ST or Samsung is committed in offering 28nm FDSOI as a 

foundry service. I am still not convinced. Please read my 

third paragraphs above.

 

Please just state your technical views on FDSOI. This is not 

a forum to give and receive advices from you. 28nmFDSOI 

requires a 7nm thin SOI channel thickness as stated above. 

With the transistor on how the electrons and holes can drift 

or travel from the drain to the source without scattering at 

the gate oxide surface at the top and the SOI oxide at the 

bottom in such 7nm thin SOI channel layer? I presented 

QM effects at the 3nm node as the end of scaling, not to 

scare people. 

 

This could be a simulation result on 28nmFDSOI. 28nm

FDSOI is not scalable to 22nmFDSOI. See my third 

paragraphs above. I don't see why Samsung would invest 

in 28nmFDSOI that is not manufactured yet and not 

scalable. Lets wait and see. 

 

No comment except that I would like to clarify one point. 

I did not say "there is no technology limitation that you 

want to solve with a FinFET that is scalable to the end of 

roadmap". 





AKH0
User Rank
Manager
Re: 28nm FD-SOI
AKH0   7/30/2014 1:18:40 PM
NO RATINGS
Dear Sang Kim,

I am afraid you have mixed up many things. PDSOI has been in production at IBM down to 22nm. It has served IBM and other companies (AMD, Freescale, Sony, Nintendo, and Microsoft to name a few) for several generatios. So, unlike what you claim it is actually scalable. Even "the one time thing" long channel devices (180nm node) are being manufactured at a handful of foundries and are powering RF parts of nearly 50% of cell phones!

Samsung reported their 20nm bulk planar at IEDM 2011 (6 months before Intel's 22nm) and at smaller gate length, gate pitch (80nm vs 90nm) and metal pitch (64nm vs 80nm). Contrary to what you say, leakage was ok, down to 1nA/um for nominal gate length. TSMC also developed their 20nm node, and although they did not report device performance in public, customers like Qualcomm have already announced their product shipment plan. So, yes bulk planar is also scalable.

I cannot speak for ST or Samsung, but what I have seen in their announcement is that they are commited in offering 28FDSOI as a foundry service and that is happening even if you are not convinced.

With all respect, I would suggest that you through away anything you have heard about device physics, mobilit, etc and start afresh. There is no mobility degradation due to the prsence of back oxide interface. Quantum effects are not a monster to be afraid of. They are in play in any device and people have been accounting for those for many years. Those publications that reported mobility degradation in thin channel FDSOI only showed a modets 10-15% degradation in peak mobility down to any channel thickness of interest. Still those mobility numbers are almost 3X higher than typical numbers you get in the prsennce of high-k! So, the back interface is not a concern, certainly not at 5-7nm  that is used in any FDSOI technology.

28FDSOI has already showed performance advantage at circuit level over 28nm bulk. Otherwise why would Samsung invest in it?

The "end of roadmap" and technology scaling has nothing to do with the gate length. A 3nm node does not have a 3nm gate length, the same way that Intel's 22nm has a gate length of 35nm. All you need for the gate length is that it fits the gate pitch. That's why practically it has been not scaled since 65nm node. At some point you need to start scaling the gate length but cerytainly no one in right mind would go less than about 15nm. After that there are several possibilities. One is monolithic stacking of 2 or more transistor layers. The other is to use vertical channel devices to decouple gate length from gate pitch. Both of these have been practiced in NAND flash and there is no reason they cannot be used in logic. Although logic does not enjoy the uniform layout that memory has.  So there is no technology limitation that you want to solve with a FinFET that is "scalable to the end of roadmap". It all boils down to whether you can do any of these cost effectively. The major problem in advanced nodes is not the choice of transistor, it's how to make three contacts to each transistor. At 10nm you need 8 mask levels just to get from the transistor to M1 (which is another 3 masks to print). How does the choice of FinFET vs FDSOI affect this esclataing cost?

 

  

michigan0
User Rank
CEO
Re: 28nm FD-SOI
michigan0   7/30/2014 3:11:35 AM
NO RATINGS

Sang Kim

 

IBM invented PDSOI, FDSOI and ET(extremely thin) SOI over

a decade ago. But PDSOI with a gate length of hundred 

micron meters was only manufactured but not today because 

PDSOI was not scalerable. It was just one time thing. You say 

"Samsung and others made 20nm bulk planar and showed their

results." What  are their results? The results are short channel 

effects or unable  to suppress the transistor leakage current. 

TSMC is said to manufacture 16nm FinFET this year or early 

2015, not 20nm bulk this year. You say that FDSOI products 

have already made by ST. and  Samsung a member of ST 

alliance is now committed to offer 28nm FDSOI to the public? 

That will not happen because  for 28nm FDSOI a 7nm thin SOI 

channel thickness is required. However, transistor performance 

becomes significantly degraded due to the transistor mobility 

degradation because of scattering of charge carriers at the top 

gate oxide surface and at the bottom SOI surface in the 7nm 

thin SOI channel. As a result, even if the 28nm FDSOI were 

manufactured today, it wouldn't be superior to the 28nm bulk 

in terms of the transistorperformance and manufacturing costs 

due to higher SOI wafer costs. The keypoint here is that the 

volume manufacturing of 28nm FDSOI was put on hold not 

because customer did not demands, but the poor FDSOI 

performance. These are the major reasons why 28nm FDSOI is 

not manufactured today. Based on Intel 14nm FinFET 

announcement, Origan fab is manufacturing 14nm FinFET in low 

volume, but not yet in huge Arizona fab that was built solely for 

14nm FinFET production. Surely there may be some delays.But 

Intel will be the First for mass production of 14nm FinFET just as 

done for 22nmFinFET. Yes, there is "end of roadmap". The end  

of road map is determined by device physics, not by the 

financial sense. 5nm channel length or gate length, Lg will be 

the end of roadmap or the end of transistor scaling because for 

3nm Lg the quantum mechanical confinement of charge carriers 

occurs. It means that electron and holes don't behave like

particles any more, instead behaving like waves in the 3nm Lg. 

As a result, the particle based classical Maxwell-Boltzmann 

statistics are no longer applicable, instead subjected to the 

quantum mechanical Heisenberg uncertainty,meaning large 

variabilities in the transistor electrical transfer characteristics 

such as Vt(increase), DIBL, Id/Vg and Id/Vd....etc. Intel FinFET

will be extended to the end of roadmap.





AKH0
User Rank
Manager
Re: 28nm FD-SOI
AKH0   7/26/2014 1:25:48 AM
NO RATINGS
IBM's 22nm which is used for power8 is PDSOI, which is very similar to bulk planar in terms of scaling and in fact uses a gate length shorter than Intel's 22nm FinFET. Samsung and others made 20nm bulk planar and showed their results. ISDA's 20nm was shown in at VLSI 2012. TSMC is said to ship 20nm parts this year. The problem with 20nm was not scalability, it was cost. For your information foundry's 20nm uses 64nm metal pitch vs Intel's 80nm. Which means foundry is offering a denser technology, which of course comes at the cost of double patterning. FDSOI products have already made by ST, see for example NovaThor demo in early 2013 that clearly showed SOC benefit. Samsung is now committed to offer 28FDSOI to the public. I do not understand your repeated comment about 28nm bulk planar being in high volume for several years as a drawback of FDSOI. Yes, 28nm has been in production for several years, but it didn't come with all bells and whistles at the beginning. The first products used poly SiON gate stack and no strain element to keep cost down. Overtime several versions of the technology with different cost-performance trade offs were offered. They are put into volume manufacturing when fabless companies demand a certain performance and are willing to pay for that extra cost. 28FDSOI is no exception to this. Volume manufacturing was put on hold because customers did not demand. BTW, Intel's 14nm FinFET is not in manufacturing yet and there has been multiple delays. And there is no such thing as "end of roadmap". Technology is scaled as long as it makes financially sense to do so. Whether it's being conventional scaling of the transistor, being stacking in 3D, or a completely new technology the same way BJT was replaced by MOSFET logic.

michigan0
User Rank
CEO
Re: 28nm FD-SOI
michigan0   7/26/2014 12:37:42 AM
NO RATINGS

Sang Kim

 

The 28nm planar bulk has retrograde and halos as you pointed 

out, but ends at the 28nm node. FDSOI is worse because 

FDSOI is not manufactured at any technology node yet as I

pointed out in my original post. Intel, IBM, TSMC and others 

attempted to extend the planar bulk to the 22nm node, but 

were not successful because of the short channel effect or 

unable to suppress transistor leakage current. Intel finally 

developed its first FDFinFETs at 22nm, and its 14nm FinFETs

are in high volume manufactured today. FinFET technology  

can be extended to the end of roadmap.



AKH0
User Rank
Manager
Re: 28nm FD-SOI
AKH0   7/23/2014 7:06:20 PM
NO RATINGS
No, the doping is not uniform in bulk planar! The well is retrograde (although not ideal) and there are halos. The whole point is that the well and halo doping will take care of leakage at the depth and gate takes care of it at the surface. I agree with you that the ideal supersteep retrograde will end up with high drain leakage, but that's not the case in FDSOI because drain is isolated from the substrate by the BOX.

BTW, your point about Vt being higher and more variable in a retrograde well is not correct either. In fact it's the other way around! Please see page 230 of Taur and Ning's text book. With retrograde well design Vt is lower than a uniformly doped well and in the extreme case independent of the well doping. This is in fact what SuVolta is promoting. Of course, with Vt being independent of the well doping you cannot use Vt adjust anymore and need to rely on body bias. What FDSOI does is simply making an ideal retrograde well possible and allowing the well doping to have either n+ or p+ polarity for either NFET or PFET witout fearing about drain leakage.

 

 

 

 

 

 

michigan0
User Rank
CEO
Re: 28nm FD-SOI
michigan0   7/23/2014 6:39:41 PM
NO RATINGS

Sang Kim

 

28nm planar bulk that is in mass production today for several 

years has uniform doped substrate that provides a fixed Vt  

and fixed depletion depth determined by uniform substrate 

doping. In a bulk planar device with super steep retrograde 

well, Vt could be higher and variable, and the gate depletion  

is blocked by the well doping, not by current flow. The current 

doesn't flow in the well unless hot carrier effect. The current 

flows from source to drain. Furthermore, the drain electric

field will be significantly higher in the retrograde well. As a 

result, hot carrier induced device failure could be higher.

 

First, the planar FD-SOI is not manufactured at any technology

node yet. Why? The un-doped 28nm FD-SOI requires an ultra-thin SOI channel, for an example, a 7nm for 28nm FD-SOI. My 

question is how the ideal super steep retrograde process can

be implemented in the 7nm thin SOI channel? It appears that

the un-doped planar 28nm FD-SOI is stilll not manufacturable.




Page 1 / 3   >   >>


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