Strange enough Intel (and TSMC) are thinking the opposite about FD-Soi.
On Intel 22nm the FinFet adoption only charge 2-3% of more costs, FD-Soi was not utilized because means a strong 10% charge over bulk.
The real story is that Samsung has not a good experience in processes for CPUs, GPUs or SOCs. Samsung has never developed something of exciting in this segment, it's processes for SOCs are licensed from Common Plataform (IBM mainly). in this moment Samsung is in crisis because IBM is out of the game and GloFo has not money to develop anything.
The more easy street to gain a bit of power reduction is to license (again) a process from another Company out of Common Plataform...
Samsung is late on 20nm bulk and likely is VERY late in FinFet, so an expensive FD-Soi could be an interim solution for it's SOCs. Too bad Samsung is losing the shrink and this will rise the costs even more. Too bad "money" is not enough to gain proof in silicon science, it needs "men" and their experience, Samsung has not them.
I can see only two companies able to gain a lot of momentum in silicon industry in the near future: Intel and TSMC.... all others have not the experience to face the upcoming very difficoult silicon nodes.
Did Intel fabricate either bulk 22nm to proove FinFET was only 2-3% cost addrer? Did they run FDSOI to see it is 10% cost addrer? No, it was all powerpoint. Same as the famous chart that claimed 37% performance advantage coming from FinFET with no silicon data to back it up -- yes, they actually showed ring ocsilator data at VLSI to support that claim, but I am sure they wish they didn't.
In principle it is possible, but it comes at the expense of less design flexibility. The gate and metal pitch at 28nm allows bidirectional poly and metal, whereas Intel's 22nm is unidirectional. A bidirectional M1 is almost equal to 2 layers of unidirectional metal for most designs.
It would depend on the design, but 28nm FDSOI should be pretty comparable to 22nm bulk planar (maybe even better?) from a power vs. performance standpoint. Die size will be bigger, which normally means higher cost, but in this case that isn't so clear. Based on the releases so far the argument in favor of the 28nm FDSOI is that for medium-low TAM products 28nm cost is a sweet spot, there is minimal re-design/re-optimization cost to go to FDSOI, so that offsets the additional substrate cost. The process flow might be a little simpler with FDSOI than with 28nm bulk planar and certainly simpler than 22nm, further offsetting the cost. I haven't seen any indication yet that they will introduce additional body biasing techniques for this 28nm node, but they could and that would further reduce power for some products. Keep in mind Intel has high TAM products that require very high performance- FinFET/TriGate has an advantage there.
@OtisTD: Actually, 28nm FDSOI comes with full body bias capability and it is one of its selling points. While people might consider body bias as an extra design burden, many companies - including Samsung in their 28nm bulk - already used static body bias. Dynamic body bias is a bit more involved but it has been done in the past (TI 45nm e.g).
When I said, I hadn't seen any announcement of "additional body biasing techniques" I meant in addition to what is already available for 28nm bulk. Are you saying that they are offering dynamic body biasing (and where did you see that)? Or just that static body biasing will continue to be offered- which was my intention/understanding. Sorry if I wasn't clear, but I didn't think it was necessary to go into detail. Basically from my understanding they will use the same masks as much as possible and directly port it over FDSOI without adding any additional performance knobs like dynamic biasing.
This post is so biased it is difficult to believe.
Saying Samsung is unable to shrink silicon technology when they are leading DRAM and Flash scaling is a joke. Not to mention there lead in display technology. But you may not consider this as "silicon".
Playing the FD-SOI card has nothing to do with failing FinFET. It has specific attribute specially for SOCs and low power technology. And this is where the future of silicon technology will be.
Before considering the fail of FinFET integration within Samsung, just wait by the end of the year...
@OtisTD: Thanks for clarifying. The 28FDSOI is using the flip-well concept (n-well under NFET and p-well under PFET) for LVT devices. RVT is same as bulk design. This allows LVT devices to be forward biased to 1V or maybe more, which is not possible in bulk. If you already have a 28nm bulk design, for static body bias, you can probably just change the well masks, drop the Vt adjust masks, and add the No SOI mask (for diodes, etc).
As far as I know, ST has already implemented dynamic body bias. While it needs some redesign and proper system and software, it is not that different from DVFS to implement. Actually it is a bit simpler because wells do not draw as much current as Vdd does, so charge pumps are enough and routing is easier.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.