I think there is still the issue that the foreground and background states drift differently, and (generally) inconsistently. The driving or starting condition for the drift is hard to repeat; sometimes the drift will be slower, sometimes faster.
Resistion:- Drift is one of the many PCM problems that I hope the authors of the VLSI paper will discuss in relation to independent foreground-background operation. As I suggested they can tap the expertise in IBM Zurich for help in the matter of drift. My brief was to try and explain how they might have achieved the 4-bit per cell results they are claiming, so let us be a little careful discussing my speculative assessment until we see the full paper. Unless that is readers want to suggest other ways in which independent foreground-background operation might be achieved in a PCM cell with 4-bit discrimination.
The key will be understanding exactly what is described in the abstract as "stressing the memory cell with current" means and what it does to the material. The other sliver of pre-information is it shifts the reset threshold. I hope it is temporary structural/charge storage, rather than a thermal effect. I did look at the possibility that independent foreground-background operation could be linked to the work of the other IBM paper and the effect strain could somehow be used as a means of temporary RAM-like storage of the background state, I was not happy, or at least my explanation of how it could be achieved. We will see.
DrFPGA-Yes you do. My piece has a considerable amount of speculation as to how I think the performance that will be reported might be achieved. Only a view of the IBM papers will prove if I am right or wrong. So you should already be booking your air ticket to Honolulu.