Thanks for the great write-up. I am very excited for this workshop given the interest expressed at the IEEE P802.3bs Task Force Meeting in May, where an effective lane rate of 100Gb/s clearly had the most interest.
This has the potential to be a defining moment in the development of network technology.
It's always the same story, Rick. The standard usually starts out with a single serial link, then to support faster speeds, it parallels several of the old serial links. Then a faster single serial is developed because multiple parallel ones become a problem to synchronize. Then speeds go higher still, and this newer serial link is again connected in parallel.
You can see this in optical and copper interconnects. In fact, 10 Gb/s Ethernet allows both single and parallel link options even for fiber optic links (where coarse WDM is used to create the parallel lanes, e.g. 10GBASE-LR compared with 10GBASE-LX4). Happens over and over again.
Single lane beats parallel lanes, but requires faster electronics and, at these speeds, would require exclusive use of single-mode fiber to achieve any range at all.
The response below doesn't seem in line with where Ethernet has gone. First, i haven't heard many individuals refer to 10GBASE-LX4 as a success. Next while it is true that 40G was based on an aggregate of 4x10G, i.e. a prior speed, that is not what happened at 100G. While 100GBASE-SR10 used 10G, -SR4, -LR4, and -ER4 are based on 4 lanes of 4x25G. Furthermore, syncronization was solved via lane markers with the IEEE P802.3ba standard.
THe jump to a 100G serial speed at this time is a very significant one. SO while you are partially correct with the mix of serial / parallel speeds, we are somewhat more challenged this time to jump to the next serial speeed.
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Perhaps you want to consider coming to the workshop. I am chairing the session on the technical issues related to coming up with a solution. More information can be found on the Ethernet Alliance / OIDA workshop at http://bit.ly/1fNDC8q.
thank you John for teh invitation...I was invloved in 10 GHz circuits design while back but for years doing something very different so will have to pass...good luck in designing this, amazing challenge! Kris
I agree Bert and would even go father...100Gb/s single lane is mission impossible...high-speed IO speeds do not follow Moore's law, I am sorry...there is no way you can design 100 GHz CDR in CMOS, even at 7nm...Kris