Came across this article while browsing for engineers sharing similar experiences in PCB reverse engineering with regards to re-creating the schematic diagram. Found it kind of interesting that the author used TinyCAD, which is kind of limited but I guess you can't expect too much from a free software, so long as you're happy and apt with using it.
My preference is to use Visio to re-create the PCB layout and the schematic diagram. I've been doing PCB reverse engineering for over 15 years in the course of my work and I like Visio because of it's versatility and support for multi-page drawings.
I've just completed writing my first book and it's available on Amazon under the title: The Art of PCB Reverse Engineering. You can also visit my website to find out more.
Ps: Max, I also recommended your book Bebop to the Boolean Boogie in my book in the Advanced Topics chapter under the topic I named The Matrix. Kinda cool, huh?
And Jim, I happened to mentioned about my 3-day stint with Daisy/Cadnetix's Daizix simulation tool running on a Sun Microsystems workstation too. Those were the good old days...
@ antedeluvian Do you ever have a call to reverse engineer programmed logic
Only once, an FPGA was being discontinued but the supplier had a new replacement version in the same package, and also the tools to convert the old programming to the new device. It did not work, and because our employer had purchased the product line from an earlier defunct company we did not have any of the original design files.
My colleague knew how to convert the program files to a readable schematic (he was the digital half of our team), and i noted that the converted schematic had eliminated buffers in several circuits - the conversion tool thought we did not need multiple buffers in series. I took one look at the original schematic and realized the multiple buffers were being used as delay elements in ring oscillators; obviously when the conversion tool removed all that 'useless' delay the oscillators stopped working.
An over-ride to the default extraneous buffer removal option of the conversion tool solved the problem. I wrote about this in more detail in a Scope Junction blog, but...
I have done a little reverse engineering, and I must say I admire your systematic approach and obvious patience.
Do you ever have a call to reverse engineer programmed logic like PLDs and/or micros. If so how do you go about reversing that? I once had to reverse engineer an 8048 based paging system in order to add a few functions. It was pretty difficult even with an emulator, trying to find the hooks to add the additional code. These modifications happened quite often and finally the customer came up with the source code. That made my life much easier.
Which merged with Cadnetix to become Dazix - now there's a winner of a name for you - not! Max was there way back when.
Glen, I take it you don't often (ever?) have the PCB layout file to work with? If you did, you might have a reason to generate a netlist. Checking the schematic-generated netlist versus the layout-generated netlist would be one more layer of idiot-proofing. I do as much idiot-proofing as is practical because I'm usually the idiot!
I'm reminded of a Dilbert cartoon in which Dogbert tells a caller to his tech support center, "Yes, our software is idiot-proof. The fact that you bought it is proof you're an idiot!"
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