Intel already made the decision to not use EUV for 10nm. EUV definitely isn't anybody's Plan A. For all Big Three (Samsung, TSMC, Intel) Plan A is to rely on SADP (self aligned double patterning). They worked on it for many years now and it is ready for HVM. Cost isn't what one would wish but, well, it is doable and still profitable. EUV is Plan B and will be used if and when ready. So the clock is ticking for ASML because time is money. Each year they spend roughly $1B on EUV R&D and with each year passing w/o HVM orders the window of opportunity is shrinking. ASML NXE3100, which each major chip maker already has in their R&D fabs since 2010/11, can produce about 5 wph, when it is able to run, which is 50% of time on average, instead of the original 60 wph specification. The NXE3300B introduced late last year was supposed to deliver 120 wph but when tested could produce only about 2-3 wph initially. ASML claims they will bring it up to 25 wph by year's end, which seems very unlikely given the technical issues they face and their history of meeting spec committments to date. Now ASML is talking about the need to completely redesign the source AND the scanner in order to be able to reach beyond 100wph, which is really a must for any HVM use. This is a major overhaul, a surgical operation on a patient which is in a critical and unstable condition. Even if patient survives, the redesign is likely to double the already sky-high current $150M a piece price of the tool.
Well....in my knowledge Intel has done the 10nm libraries for both EUV and 193um immersion steppers. All depends on ASML, they must to sell reliable EUV steppers with the same per hour output of actual equipment....instead of Intel and TSMC will go straight to quadruple patterning, there is no plan B.
These boring considerations about costs are only a manner to hide the real story: EUV is LATE and a 200 wafers/hour output with a charge of 20/30% is far better than a ridicule 50-100 wafers/hours with a charge >100% (time is money and ASML has forgotten this and the Companies can not double the investiments to have the same output). Moreover we don't know anything about the reliability of these new steppers, Intel and TSMC have a lot of money in ASML and sure they know what is better.
The cost of silicon will go up and the times of cheap SOCs and FPGAs are ending.
Who manufacture with the higher gross margin will suffer less.
Rick, I get the sense from the article that Moore is on shaky ground going forward. We've heard that before but seems like barriers, although not necessarily insurmountable, are incurring escalating costs. Small transistor sizes mean more transistor on fairly large die, already in the billions, smaller die for a given number of transistors, lower power and, or higher speed.
Especially in the limits of large die scenario it might be time to look into solving thermal, interconnect and signal integrity issues in multi stacked layers.
In a way this reminds me of the clock rate vs thermal limit we faced many years ago, the answer was not a relentless drive to higher frequencies but a turn to parallelism. We need to understand the fundamental nature of the problems we are trying to solve and go about them with more intelligence and less brute force.
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.