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Max The Magnificent
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Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 1:22:15 PM
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@DrFPGA: The future is in your hands...

I just have to remember to make sure I use my power only for the good :-)

DrFPGA
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Re: Helping in tackling obsolescence
DrFPGA   6/23/2014 1:07:48 PM
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The future is in your hands...

Max The Magnificent
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Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 12:39:17 PM
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@DrFPGA: SoC, SoC FPGA, ASIC, ASSP- how my hear hurts. I think you may need to do another blog on the alphabet soup we have created around our various Programmable Logic Devices...

Actually, that would be a good one -- leave it with me :-)

DrFPGA
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Re: Helping in tackling obsolescence
DrFPGA   6/23/2014 11:49:03 AM
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SoC, SoC FPGA, ASIC, ASSP- how my head hurts. I think you may need to do another blog on the alphabet soup we have created around our various Programmable Logic Devices...

Do you have a taxonomy you feel strongly enough to blog about? Maybe we need to put naming things back in the hands of engineers and take this mighty power away from the marketing types...

Max The Magnificent
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Re: Efficiency
Max The Magnificent   6/23/2014 9:42:14 AM
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@DrFPGA: The 128byte FIFO and the hardware support for CTS/RTS...

It's funny -- we're so used to thinking in terms of megabytes and gigabytes (re a computer's main memory) that we forget how much difference a few bytes can make in something like a judiciously-placed FIFO

Max The Magnificent
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Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 9:40:16 AM
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@Sanjib: I guess another advantage of such IPs getting available for FPGA/SoC platforms...

It also makes it easier to prototype in an FPGA before committing to an SoC

Sanjib.A
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Helping in tackling obsolescence
Sanjib.A   6/22/2014 2:18:45 AM
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I guess another advantage of such IPs getting available for FPGA/SoC platforms would be to make life easier for tackling obsolescence of the original ICs. By making the clone of such popular but matured ICs based on programmable platforms, it helps in reducing the re-design efforts for extending the life of the product for much longer period and makes the development cycle shorter.

DrFPGA
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Efficiency
DrFPGA   6/12/2014 4:38:08 PM
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The 128byte FIFO and the hardware support for CTS/RTS (that keeps the CPU from neededing to take action) are excellent efficiency enhancers. I just want the data to flow with as little CPU intervention as possible. Just set-up the buffer and go do something else. Cool.



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