The 128byte FIFO and the hardware support for CTS/RTS (that keeps the CPU from neededing to take action) are excellent efficiency enhancers. I just want the data to flow with as little CPU intervention as possible. Just set-up the buffer and go do something else. Cool.
I guess another advantage of such IPs getting available for FPGA/SoC platforms would be to make life easier for tackling obsolescence of the original ICs. By making the clone of such popular but matured ICs based on programmable platforms, it helps in reducing the re-design efforts for extending the life of the product for much longer period and makes the development cycle shorter.
@DrFPGA: The 128byte FIFO and the hardware support for CTS/RTS...
It's funny -- we're so used to thinking in terms of megabytes and gigabytes (re a computer's main memory) that we forget how much difference a few bytes can make in something like a judiciously-placed FIFO