Being fabless Qualcomm knows that its main problem, in the near future, will be the interconnection and the adjustment of a given process to a specific design (or otherwise). Unfortunately this company can not dictate the best solution but it must wait instead the choices of foundries. In spite of the very recent fortune of the fabless + foundry model, paradoxically the IDM model will be the must in the next years as the new nodes will become a real challenge. I think that there will be a profound change in the semiconductor industry in upcoming years.
Yes, "Qualcomm has got the problem" and so is any semiconductor, fabless or IDM, that is selling to price sensative market and far more so if part of its sells comprise upgrades that might not happend if the price is not attractive.
Qualcomm is large enough and with its $16B on its balance it could afford to buy a fab or a partnership into a fab if that was the problem. Samsung would not have bothered in going back to develop FD SOI on 28 nm if they were not being concern with the same issues Qualcomm is.
I don't agreed with you about IDM, in a far more comfortable situation versus fabless. All fabless contenders are at least one year late on 20nm (pretty inferior to the 2.5 years old Intel 22nm, from the point of view of performance and power consumption)
Still...yes Qualcomm/Apple are rich enough to have a fab(s) but this means more costs, more staff, more risks, less net profit. The last part of my post is to say that times of "easy huge profits" are ending and fabless manufactures need to change their businsess model. It's too easy to blame TSMC or GloFo for low yields......come on! put the money on the table to develop the right process to do better SOCs and modems!!!!!. Nvidia and Amd too are laughable with their lamentations about the new TSMC planar process; they want to make the designs without spending nothing for the process development. This is the end of an era IMO.
Note in the 3rd picture, the 20nm process node that uses double patterning, is still on the cost trend. This differs from other sources that continue to claim 28nm is the lowest cost node. So the final cost ended up being lower then expected. Perhaps 16/14nm will still follow the cost trend?
Yes most sources are along the lines of the fourth picture. In the third picture, they have 22/20 as the last node. That would only make sense if they had only a few mask adders for double patterning, or if they had relaxed design rules to begin with (but using the most advanced transistors).
Regarding the statement ""Mobile is becoming a centre of gravity for the user...," it is true to a large extent but not quite the complete picture. More rigorous computing and storage is at the cloud layer for these types of mobile-centric use cases. Therein, M3D makes more sense in mobiles than in those in servers and switches at the cloud layer. Nonetheless, if M3D progresses to a state where it is cost-competitive and yields are proven, there is definitely opportunities for fabless / IDM companies to innovate. But I see this as still way out in to the future. In the interim, 2.5D/3D stacking is here to stay!
This just confirms that Qualcomm's own effort to do 3-d stacking of chips using TSVs has bombed out. So now they want to switch horses to stacked transistors. The question is who is going to foot the R&D bill ? The fabless wonders have made themselves very attractive to Wall St by using technology developed by IDMs in the US which then "diffused" to off shore Foundries through various "channels". Are fabless chip vendor like QCOMM going to subsidize any of the R&D for 3-d stacking of xsistors ? Is Wall st. going to let them ?
Zvi what do you think TSV based 3-d stack does to RC delay off chip ? Just the same as on - chip and this is really the main driver for using TSVs in the context of SoC - DRAM combinations
French Govt. funded LETI too started with using TSVs to integrate SoC s to DRAM. After buiding and evaluating some simplified TVs including using a SoC of their own design, they too have backed off and then just a couple months back ( soon after Samsung started reporting their 3-d NAND ) started publicizing a change in direction to monolithic 3-d stacking of transistors.
If you have following reports in EE Times etc. its only after that QualComm started showing interest in 3-d stacking of transistors perhaps even for some super - large SoC of the future with zillion cores.
If you are privy with any actual support by Qualcomm of the recently initiated LETI R&D on monolithic 3-d stacking of transistors as you claim, then pray share it with the rest of us.
We of course wish your own company such windfall for your own R&D.
Thank you for the support. I agree that TSV has the potential to reduce significantly the off chip interconnect and accordingly provide are real reduction in power and increase of speed for most system out there. It also seems that the slow adaption of TSV is not due to technology challenge but rather the high cost associated with it.
But this has very little to do with monolithic 3D as those technologies complement each other rather. I believe that there is clear evidence out there that the interest in monolithic 3D is not the result of issues with TSV but far more with issues with dimension scaling. Dimension scaling while still going on had stopped providing the traditional cost reduction it once did. The delays in EUV make it clear that these are not a short time hick-up but rather a paradigm shift.
It is clear to me that the industry need to put far more efforts behind monolithic 3D as continuation of cost reduction would be critical for the industry ability to fulfill the promise of the emerging market of IOT and wearable.
The question regarding cost reduction for monolithic 3D is a good one. We have devoted a section on the MonolithIC 3D web site to present it, titled - 3D-IC Edge - http://www.monolithic3d.com/3d-ic-edge1.html. I believe you will enjoy reading it and I hope to get inputs for additional advantages.
The 3D NAND, which is now in mass production, is a good example for the cost reduction enabled by monolithic 3D, as multiple layers are simultaneously processed providing road map for cost reduction by scaling up.
most always its technology challenge that raises the cost of using it. for the most part the most common process flow & materials for TSVs have been stuck in a blind alley - a consequence of amateurs getting too excited with PowerPoint engr.
@chipmonk: I like your statement "amateurs getting too excited with PowerPoint engr!" For the most part, it has been like that. There are however some products that are seeing some commercial success (like Samsung's memory products). Perhaps some one from Samsung can share something here on the cost reduction roadmap for TSV-based products in the future.
As far jumping on Qualcomm's bandwagon on monolithic IC and going along for the ride, there are definitely risks involved (as seen by some who rode Q's TSV bandwagon in the past! Javelin any one?!!)
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.