A lot of engineers still use active-low signals in HDL, which drives me nuts. It just adds confusion, and isn't really helpful unless you accidently time-warp back to 1982. Then when they OR them together they'll DeMorganize which makes everything more confusing:
Ahhh the memories.... That was required reading in one of my EE classes at Cal Poly (mid '80s) I had never dreamed there would be so much intrigue and espionage in the design of a computer. I recall that GI was one of the first to utilize PALs.
I believe the origin of the asymmetry traces back to relay logic. Relays were either on or off (subtly different from high or low) and that conditioned the way of thinking about logic. It suited bipolar transistors very well, especially since they could only make NPN on the chip in the early days (to do both would add process steps). Well, they could have made a chip with all PNP but that performed worse then as they still do today, so TTL was all NPN and engineers could happily continue in the mindset of a "1" being switch on, pull down. There was not much concern about capacitance so pull-up current could be low. External wires themselves became extra logic (a bus line served as a "wired NAND" when it had a pull-up resistor).
CMOS was exotic technology requiring the chip to go through extra process steps. The first forms which came out in the early 70s were aimed at low power and almost seemed like magic (they ran on less than a micro-amp!). But even these, initially, had the same asymmetric ability to sink 20mA (a standard which went back to teletypes and relays) with very little pull-up (which was fortunate since the PMOS transistors, like PNP, were lower performance than NMOS). It was not until the late 80s when CMOS was pervasive and wired-NAND style busses finally died in pursuit of higher frequency / lower power operation that CMOS outputs became routinely symmetric and the idea of pull down faded entirely.
I'm pretty sure that version with zener diodes must have been a very late iteration of TTL. I recall zeners being a novelty in the early 70s as discretes, and it probably added complexity for them to learn to make them on the same chip as the transistors.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.