Texas Instruments was not the earliest semiconductor company to promote the use of multiple emitter transistor coupled coupled logic circuits. A small semiconductor company in Calif. called Pacific Semiconductors Inc.(PSI)1st developed transistor squared logic (T2L)circuits in early 1961.The company competed with T.I. for an Air Force contract for the tri-service (TFX) fighter electronics. T.I. won, and PSI was subsequently aquired by Thomson-Wollridge (TRW).
The resistor coupled logic (RTL)circuits had a noise immunity problem with the "bottle geometry" if the base resistor was integratef with the transistor.Tsquared logic circuits had a high transistor leakage characteristic because of the "inverse beta" of the coupling transistor unless special processing was used in the construction of these devices.
Don Schulz P.E. (retired)
ex PSI, TRW employee.
While the pull-up transistor in the TTL totem-pole output stage is stronger than RTL's resistive pull-up, the pull-down transistor is typically 40 times stronger that the pull-up. IIRC, a standard TTL output can sink 16 mA but source only 0.4 mA. That's OK if you're driving other TTL gates, since TTL inputs have the same 40:1 asymmetry.
The asymmetry meant that TTL-based designs almost always used active-low drive for LEDs and active-low push-buttons. Nowadays CMOS outputs are generally symmetric, but old-timers like me still prefer active-low if an output needs a lot of current.
Developments never make fundamentals old, these things are still being taught the way they are in the curriculum in many countries. And it really helps to explain and test the small circuits, as a stepping measure to bring the students at the current technology usages.
A lot of engineers still use active-low signals in HDL, which drives me nuts. It just adds confusion, and isn't really helpful unless you accidently time-warp back to 1982. Then when they OR them together they'll DeMorganize which makes everything more confusing:
I believe the origin of the asymmetry traces back to relay logic. Relays were either on or off (subtly different from high or low) and that conditioned the way of thinking about logic. It suited bipolar transistors very well, especially since they could only make NPN on the chip in the early days (to do both would add process steps). Well, they could have made a chip with all PNP but that performed worse then as they still do today, so TTL was all NPN and engineers could happily continue in the mindset of a "1" being switch on, pull down. There was not much concern about capacitance so pull-up current could be low. External wires themselves became extra logic (a bus line served as a "wired NAND" when it had a pull-up resistor).
CMOS was exotic technology requiring the chip to go through extra process steps. The first forms which came out in the early 70s were aimed at low power and almost seemed like magic (they ran on less than a micro-amp!). But even these, initially, had the same asymmetric ability to sink 20mA (a standard which went back to teletypes and relays) with very little pull-up (which was fortunate since the PMOS transistors, like PNP, were lower performance than NMOS). It was not until the late 80s when CMOS was pervasive and wired-NAND style busses finally died in pursuit of higher frequency / lower power operation that CMOS outputs became routinely symmetric and the idea of pull down faded entirely.
I'm pretty sure that version with zener diodes must have been a very late iteration of TTL. I recall zeners being a novelty in the early 70s as discretes, and it probably added complexity for them to learn to make them on the same chip as the transistors.
The asymettry persists to this day in CMOS MCU's , typically a 4:1 or 10:1 asymettry on the pins when configured as outputs. This has a lot of advantages:
Much more common to short a signal wire to ground (harmless with soft pull up)
You don't have to run 5v to your switches (and risk shorting that to ground)
You bolt together 5V CPU's (with a 1.6v threshold) with 3.3v CPU's (with 1.6v threshold)
You can drive a LED to gnd directly from a CPU pin without a resistor
Less of an issue connecting together two devices, where the 5V on each may not always be present
I'm a big fan of active low too! , this still persists other than in ULN2003, e.g. very rarely does one see PMOSFETs used in 100v + power applications, so you are generally stuck with NMOS switch to gnd circuits.
Ahhh the memories.... That was required reading in one of my EE classes at Cal Poly (mid '80s) I had never dreamed there would be so much intrigue and espionage in the design of a computer. I recall that GI was one of the first to utilize PALs.
@DouginRB.... are you aware you can change / correct your comment posts using the Edit/Delete link below your post (you have to be signed in)? However do NOT use it to get rid of great puns like that - there are a lot of us here who appreciate them!
@DouginRB....I'd love to be in So Cal having a Barbie, but I'm in Australia - a place called Bathurst inland from Sydney, It was minus 3.4 degrees C yesterday and probably about minus 2 this morning - we are in the middle of our winter. Not Barbeque weather at all..... but have a great Independence day and enjoy your BBQ!
PS I come from Rhodesia which is probably the only country apart from yours that declared independence from Britain. Ours only lasted 15 years, so you guys have done a bit better - well done!
Sheetal wrote: PCBs just used to be so crowded with these small components and how difficult it was to do troubleshooting.
Nowadays PCBs are crowded with even smaller components in 0.4mm pitch BGAs and QFNs. For debugging, it was sure was nice to be able to attach DIP clips and hook up 'scope probes to those 0.1" pitch pins...
Compelled to point out that the board pictured isn't a Nova 1200 CPU; it's too modern with the 40 and 22 pin chips! Here's a photo of an actual Nova 1200 CPU: http://imgur.com/IlWE6sK . Designed in 1970 or so, this particular board was manufactured in 1976.
The 74181 chip is top-center; the other 24pin chips are Signetics 8264 muxes to feed it. It was a brilliant design for its day. Nibble-wide processing meshed perfectly with the many 4-bit wide TTL chips available (7489 16x4 RAM, 74170 4x4 RAM, etc), and there was little speed penalty since the core cycle time of 1200ns still dominated the instruction cycle time of 1350ns.