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EmbeddedSteve718
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Nothing really new. . .
EmbeddedSteve718   7/8/2014 10:42:24 AM
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Just an updated variation of a theme:

http://en.wikipedia.org/wiki/Network_on_a_chip

3 companies listed here:  They've been around for years. . . .

ARM's Latest:  http://www.arm.com/products/system-ip/interconnect/corelink-ccn-508.php

IBM's been doing this for years:  http://en.wikipedia.org/wiki/Blue_Gene

Anyone know of Tilera (http://www.tilera.com) recently purchased by EZChip?  Another multi-core MIT spin-off.

HW is good, but being able to exploit this "correctly" requires rather smart Software that doesn't exist.  Tilera and other multi-core folks have been playing with this for years, still not there. . .  Even today, with ARM interconnects, SW can only do so much to exploit the HW.  Until HW and SW get together (i.e. make a hole in the fence) - we'll never fully utilize all the CPU power we have.  We'll just continue to waste it with more cores running crappy software. . . . 

As the Saying Goes:  "It's the software, stuipd". . . .

R_Colin_Johnson
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Re: Nothing really new. . .
R_Colin_Johnson   7/8/2014 11:14:42 AM
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Your'e right if they fail, but just like the other guys , these guys think they have the software right this time. If they do have siomething new and validate their software through testing, then they will release the Verilog hardware description, so at least they are doing things in the right order!

markhahn0
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Re: Nothing really new. . .
markhahn0   7/13/2014 2:07:53 AM
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It's funny that people always whinge about how software is the problem, that sw isn't taking advantage of the hw.  I'd like to propose the opposite: very little sw needs highly parallel hw.  As a person who works with highly parallel systems every day, I always cringe when someone asks why their desktop system doesn't run 4x faster on a 4-core system.  The answer is mainly "because you don't need it to".  Or a little less sarcastically: you have tiny sections of workload that may be inherently parallel enought to take advantage of highly parallel hardware, but most of your time is spent waiting on the user, or IO or memory.

There are plenty of workloads that can effectively utilize a 36-core chip today, AND DO SO.  Heck, 36c isn't even a bit system these days - it's doable in a simple commodity dual-socket server.  Not to mention Phi or GPUs.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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